| Literature DB >> 32232094 |
Autumn J Bullard1, Samuel R Nason1, Zachary T Irwin1, Chrono S Nu1, Brian Smith2, Alex Campean2, P Hunter Peckham2,3, Kevin L Kilgore2,3,4, Matthew S Willsey5, Parag G Patil1,5,6,7, Cynthia A Chestek1,8.
Abstract
BACKGROUND: The loss of motor functions resulting from spinal cord injury can have devastating implications on the quality of one's life. Functional electrical stimulation has been used to help restore mobility, however, current functional electrical stimulation (FES) systems require residual movements to control stimulation patterns, which may be unintuitive and not useful for individuals with higher level cervical injuries. Brain machine interfaces (BMI) offer a promising approach for controlling such systems; however, they currently still require transcutaneous leads connecting indwelling electrodes to external recording devices. While several wireless BMI systems have been designed, high signal bandwidth requirements limit clinical translation. Case Western Reserve University has developed an implantable, modular FES system, the Networked Neuroprosthesis (NNP), to perform combinations of myoelectric recording and neural stimulation for controlling motor functions. However, currently the existing module capabilities are not sufficient for intracortical recordings.Entities:
Keywords: Brain machine interface; Functional electrical stimulation; Implantable; Low power; Neural interface
Year: 2019 PMID: 32232094 PMCID: PMC7098219 DOI: 10.1186/s42234-019-0019-x
Source DB: PubMed Journal: Bioelectron Med ISSN: 2332-8886
Fig. 1Concept diagram for brain-controlled FES. The grey box denotes the existing NNP system and the red box denotes the planned novel module
Neural Recording Module Design Specifications
| Parameter | Value |
|---|---|
| Area | 1.0 × 4.0 cm |
| No. channels | 96* |
| ADC resolution | 16 bits |
| Amplifier input noise | 2.4 μVRMS |
| CPU clock | 8 MHz |
| Low-pass filter | 0.1–20 kHz* |
| High-pass filter | 0.1–500 Hz* |
| Sampling rate | 2.17 kSps (96 channels) |
| 32.05 kSps (1 channel) | |
| Supply voltage | 3.3 V |
*Configurable in software
Fig. 2Block diagram of the neural recording module. (*) indicates future work not presented here
Fig. 3Prototype board used for testing. Three panels (left to right): bioamplifiers, microcontroller, network and power circuitry
Fig. 4(Left) Example mockup of final design with flexible circuitry. (Right) Demonstration of folded board to fit within the NNP module canister
Fig. 5(Top) Surgical photo of Utah arrays implanted in the motor and sensory cortex of a rhesus macaque. A – anterior, L – lateral, CS – central sulcus. (Bottom) Spike panel recorded from the M1 array using a Cerebus Neural Signal Processor (Blackrock Microsystems) illustrating the number of single units and their quality. Data from this monkey was used in later analysis to validate the device offline and in vivo
Fig. 6Experimental Setup. a While the monkey performs the finger flexion task, broadband neural data is recorded through the Cerebus and saved on a computer. The offline data is later replayed through the module using a National Instruments DAQ card. b While the monkey sits still, neural data is recorded through the device and sent to a computer
Fig. 7Single channel data recorded through the device, sampled at 32 kSps. a 1 kHz sine wave. b Simulated neural data from neural signal generator (Blackrock Microsystems). c Pre-recorded neural data from rhesus macaque
Fig. 8Single units recorded in vivo through the device. Each channel was recorded individually
Fig. 9Power calculated from 2 kSps data offline compared to data output from the device on a single channel
Fig. 10a Comparison of mean spiking band power from the device normalized to the maximum power and firing rate calculated offline normalized to the maximum firing rate over 100 ms windows for the best single channel. b Histograms of the correlation coefficients for all channels in the dataset
Power Saving Techniques
| No. Channels | Power Mode | System Power |
|---|---|---|
| 1 | 30ksps | 31.2 mW |
| 1 | 2ksps | 22.1 mW |
| 96 | 2ksps DMA sampling + CPU awake | 45.3 mW |
| 96 | 2ksps DMA sampling + Disabled Peripherals + CPU awake | 40.0 mW |
| 96 | 2ksps DMA sampling + Disabled Peripherals + CPU asleep | 33.6 mW |