Unbiased Plasmonic-Assisted Integrated Graphene Photodetectors.

Photonic integrated circuits (PICs) for next-generation optical communication interconnects and all-optical signal processing require efficient (∼A/W) and fast (≥25 Gbs-1) light detection at low (<pJbit-1) power consumption, in devices compatible with Si processing, so that the monolithic integration of electro-optical materials and electronics can be achieved consistently at the wafer scale. Graphene-based photodetectors can meet these criteria, thanks to their broadband absorption, ultra-high mobility, ultra-fast electron interactions, and strong photothermoelectric effect. High responsivities (∼ 1 A/W), however, have only been demonstrated in biased configurations, which introduce dark current, noise, and power consumption, while unbiased schemes, with low noise and zero consumption, have remained in the ∼ 0.1 A/W regime. Here, we consider the unbiased asymmetric configuration and show that optimized plasmonic enhanced devices can reach for both transverse-electric and transverse-magnetic modes (at λ = 1550 nm), ∼A/W responsivity, and ∼ 100 GHz operation speed at zero power consumption. We validate the model and material parameters by simulating experimental devices and derive analytical expressions for the responsivity. Our comprehensive modeling paves the way for efficient, fast, and versatile optical detection in PICs with zero power consumption.

Introduction

Photonic integrated circuits (PIC)[1] can be used for interconnects,[2,3] all-optical signal processing,[4,5] as well as for neuromorphic photonics,[6−8] whereby programmable (trainable) PICs become the photonic hardware counterpart for artificial neural network algorithms. There has been continuous progress in all key performance metrics,[9] including increased bandwidth (BW),[10] reduced footprint,[10] and reduced power consumption,[10] with current transceiver technologies already allowing for 400 Gb/s operation,[3] and moving towards 800 Gbs–1 [9] and 1.6 Tbs–1 interconnect applications.[2]

With receiver circuitry forming a critical element in the landscape of PICs, this performance race confronts the photodetector (PD) technology with a challenging functionality framework. PDs must constantly aim for smaller-size layouts with high optoelectronic BW (>100 GHz)[11] and improved efficiencies (∼ 1 A/W),[12,13] while expanding along a complementary metal-oxide-semiconductor (CMOS) process compatible framework.[14] At the same time, they are required to operate at a low energy envelope, with improved noise characteristics,[10] thus making a strong case for unbiased operational schemes which have zero power consumption, zero dark current, and low noise.[15] They also need to support dynamic tunability in both photoresponse and electrical resistance, when their employment in balanced-PD schemes is targeted, i.e. paired PDs of equal response with their signal subtracted to reduce the light source noise,[16−18] or subtraction of mixed signals in coherent detection schemes.[19] Currently used bulk semiconductor technologies such as Ge[20,21] and InP[22,23]-based PDs cannot meet all these criteria simultaneously. Besides spectral limitations associated with the semiconductor band gap,[24] they often enforce process changes[20,21,24,25] or experience speed limitations due to the material intrinsic mobility and increased thickness of the photoactive layer.[26] These factors led to PD devices with increased complexity,[26] and a trade-off between operation speed and responsivity.[27]

Single-layer graphene (SLG) is ideally suited to meet the abovementioned requirements,[10,15,28−30] and a variety of integrated graphene PD (GPDs) prototypes have been demonstrated.[31−45] SLG exhibits ultrafast electron interactions (<50 fs),[46] extremely high room temperature (RT) carrier mobilities (>10,000 cm2/Vs),[47−51] CMOS compatibility,[15,52,53] field-effect gate tunability,[54−57] and broadband optical response.[28,29,58,59] On-Chip GPDs have been reported in both biased[31,34,36,40−42,45] and unbiased[34−40,44] schemes, demonstrating external responsivity (i.e. ratio of photocurrent Iph to incoming power Pin) up to RI,ext ∼ 0.7 A/W[42] and ∼ 0.11 A/W,[44] respectively, at ∼ 100 Gb–1.[31,41,45] In a biased scheme, a source–drain voltage is applied to SLG and the photocurrent is measured as the difference between bright (under illumination) and dark currents,[31] where the bright current is modulated as a result of photoconductive[36,60] and photobolometric[31,60] effects. Under bias, however, the SLG gapless nature[61] leads to a sizable dark current and increased noise,[15] resulting in a non-negligible power budget for PD operation (∼ 1 mW)[31] and for the overall power requirements.[15] Lower power metrics, on the other hand, can be accomplished when PDs operate without bias[15,28] exploiting the photothermoelectric (PTE) effect,[28,30] whereby an electronic temperature, Te, gradient gives rise to a photovoltage due to the Seebeck effect.[62] To get a net photoresponse from the device, the symmetry between source and drain contacts must be broken. This can be achieved by either an architecture supporting asymmetric light absorption,[33−35] or by an asymmetric gate creating a lateral pn-junction configuration.[36−40,44]

Unbiased GPDs reported so far have been typically augmented with absorption enhancement mechanisms to increase the SLG absorption above the 2.3%[58] it has when suspended and even lower on a substrate,[63] exploiting either photonic crystals[40] or plasmonics.[32,37,41] However, thus far, RI,ext ≲ 0.11 A/W for unbiased devices,[34,36,40,44] significantly lower than the ∼ 0.7 A/W reported for biased GPDs.[42] Given the preference for zero dark current, low noise, and low power consumption in PIC PDs, the critical question, then, is whether RI,ext ∼ 1 A/W or above can be obtained in unbiased GPDs.

Here, we show that this is possible, by analyzing the performance of a device architecture consisting of unbiased source–drain contacts asymmetrically placed with respect to a Si waveguide (WG).[33−35] We employ coupled optical, thermal, and electrical simulations, and show that the simplest design enables strong (i.e., RI,ext ∼ 1 A/W) performance even at zero bias. We provide realistic full device model and material parameters, validated by comparison to experimental results. This allows us to understand the photoresponse mechanisms, the reasons why prior art reached different results and smaller performance, and how to optimize device concepts and designs (i.e., plasmonic effects at the contact edge, WG and contact configurations, and gating profile). An analytical expression derived for the ideal PTE performance (where absorption occurs only in SLG within a delta distribution at the contact edge without metal losses) defines an ideal internal responsivity (i.e., the ratio of photocurrent Iph to absorbed power Pabs) limit up to few A/W for asymmetric-contact unbiased GPDs. We consider both transverse electric (TE) and transverse magnetic (TM) guided modes. A scan of different gating combinations shows that independent dynamic control of resistance and RI,ext can be achieved, paving the way to balanced photodetection schemes.[16−18] Noise, sensitivity, and operation speed metrics are also calculated.

Our comprehensive theoretical framework provides the understanding and guidelines needed to have tunable integrated GPDs with zero-consumption, low-noise, high-sensitivity, and high-speed operation.

Results and Discussion

We consider an integrated GPD comprising a Si WG (220 nm thick) on a silicon-on-insulator substrate, as shown in Figure . hBN encapsulation ensures high-mobility SLG at RT.[64] Two Au electrodes (100 nm thick) are located asymmetrically on opposite sides of the Si WG to collect the photocurrent assuming unbiased operation: one of them 700 nm off the WG edge, and the other at a distance d, varied between 300 and −100 nm. Two contact formats are explored: 1d edge contact[65,66] (Figure b) and 2d top contact[66,67] (Figure c). Three Si WG configurations are also explored: fully embedded[34] (Figure d), half-embedded[35] (Figure e), and exposed (Figure f). The WG width, w, and device length, L, are varied, while all other parameters in Figure remain fixed.

Figure 1

(a) Schematic device configuration with Si WG (220 nm thick) fully embedded in the SiO2 substrate (the encapsulating hBN layers are not shown for clarity). (b,c) Schematic 1d (edge) and 2d (top) contacts, respectively. (d–f) Schematics of 3 WG configurations: fully embedded in SiO2, half embedded, and fully exposed, respectively.

In unbiased metal/GPD devices, both PTE[34,68,69] and photovoltaic[68−71] mechanisms contribute to the photoresponse, depending on contact metals[72,73] and light polarization.[69,72] In an asymmetric device configuration, like that studied here, photocurrent measurements as a function of top-gate and source–drain voltages indicated PTE as the dominant effect.[34] Thus, we also assume it to be the dominant mechanism here. Its traits include ultrafast detection[36,39] and zero-bias operation,[15,28,74,75] the latter providing for low noise[10,15] and low power consumption.[10,15] The PTE effect generates a voltage drop (thus an internal field) VPTE ∝ s∇Te,[72,74] where the Seebeck coefficient, s, depends on Te and Fermi level, EF, across the SLG channel, with no requirement of a source–drain bias to observe an ultrafast response.[34,35,37,39] For obtaining a net nonzero VPTE without bias, an asymmetry must be present in s(x) or in ∇Te(x), where x runs from source to drain. The former can be achieved by a split-gate to create an in-plane pn-junction.[36−40,44] The latter, simpler and employed here, is achieved by asymmetrically positioning the contacts with respect to the Si WG.[33−35]

Full-wave simulations, for both the fundamental TE and TM modes at λ = 1550 nm, incident from the Si WG into the PD, in Figure , show the emerging optical effects as one of the contacts is brought closer to the WG. The optical mode excites and hybridizes with surface plasmon polaritons (SPP) on the Au contact edge,[33] increasing the local SLG absorption. The hybridization is seen by the beating pattern of the absorption along the WG, becoming more pronounced as d decreases, and creating a strong asymmetry in the SLG absorption profile. This increases Te locally, while close to the other contact SLG remains cold. Note, however, that roughness on the metal contact will add to scattering and propagation losses on the plasmon mode, reducing SLG absorption, thus limiting the benefits coming from the SPPs.

Figure 2

Absorption density αden (%/μm2) in SLG channel for (a–c) TE and (d–f) TM mode at λ = 1550 nm, at different d. The other contact is 700 nm to the left of the figures (not shown). The device configuration is 1d contact, w = 450 nm, L = 30 μm, and fully embedded Si WG. The white dashed lines indicate the Si WG position and the yellow bar the Au contact.

The SLG electron (e) heating and cooling dynamics can be understood as follows: light absorption creates hot nonequilibrium carriers which undergo carrier multiplication by electron–electron (e–e) scattering (τe–e < 50 fs),[46,76,77] i.e., by impact ionization (interband scattering creating new e-h pairs[78,79]) and impact excitation (intraband scattering distributing the excess energy within the band[80]) and relax into a hot equilibrium Fermi–Dirac carrier distribution at an elevated temperature Te.[46,76,77,81,82] This hot thermalized carrier distribution is established locally with one temperature (Te) and chemical potential (μ).[46,77] Local cooling of the e gas then follows, by electronic heat diffusion and electron–phonon (e–ph) scattering (τC ∼ 2–4 ps).[46,82−89] Due to the much smaller SLG electronic heat capacity compared to the ones of SLG lattice, hBN, and metal contacts,[90] the latter are assumed to remain at RT. Also, plasmonic hot carrier (HC) effects[91,92] in the Au contacts have a small effect on the PTE response (see Methods). Considering all this, heat diffusion simulations (see Methods) show that the absorption spatial asymmetry results in a Te asymmetric profile, which, in turn, gives rise to a thermoelectric voltage[74], where the integration is over the entire SLG area (length L and width W). VPTE is the device’s open-circuit voltage. The performance metric is the voltage external responsivity RV,ext = VPTE/Pin, where Pin is the incoming optical power. If the device internal resistance is RD, then the external sort-circuit current responsivity is RI,ext = RV,ext/RD. We note that in either open-circuit or sort-circuit conditions, the output power efficiency of the device is zero. We now consider the effects of WG, contacts, device geometries, and SLG doping to reach a generalized understanding of the PTE effects in integrated GPDs and, by that, an optimization framework.

We first examine the SLG EF effect. We assume it pinned at −0.15 eV at/under the contacts (because of charge flow between SLG and metal reaching an equilibration depending on the metal work function),[93] while it can vary across the channel (source-to-drain). Typically, SLG is found to be p-doped.[94] We consider 3 indicative EF = −0.02, −0.10, −0.18 eV, corresponding to extremely low, low, and average doping for hBN encapsulated SLG, respectively.[95,96]Figure a plots the distribution of Te increase within the SLG channel for a d = 50 nm and L = 30 μm device illuminated with TE polarization at 1 μW. The absorption profile is practically the same for any EF in the range −0.21 to 0.21 eV, but differences in heat capacity and thermal conductivity (see Methods) result in different Te profiles. In addition, the different EF gives different s (see Methods). As shown in Figure c,d, the profile and peak position of the thermoelectric voltage are determined by the Te gradient, while s determines the magnitude. Thus, while EF = −0.10 eV does not produce the largest Te gradient (see Figure c), it does yield the largest thermoelectric voltage due to the larger s, as for Figure b.

Figure 3

Spatial distribution of thermal quantities across SLG channel at the front (entrance) of the device for 1 μW incoming power with d = 50 nm, L = 30 μm, TE polarization, and fully embedded Si WG configuration. Solid lines correspond to various SLG EF for a 1d contact, while the dashed line corresponds to EF = −0.1 eV for a 2d contact. EF is assumed fixed at −0.15 eV under the contacts. (a) Te increase, (b) s, (c) Te gradient, and (d) local thermoelectric voltage s∇Te projected along the x (source–drain) direction. In all panels, the yellow bars indicate the Au contacts, and shaded light blue the Si WG.

The main difference between 1d and 2d contacts is that in the latter SLG extends under them,[66] providing extra space for cooling through electronic heat diffusion and e–ph scattering. In the 1d case, in contrast, the electronic heat diffusion process is terminated at the contact edge, which results in a larger Te gradient, thus higher RI,ext. Cooling can be faster (i.e., smaller τC) locally where SLG is directly contacted by Au[97,98] (due to interactions with Au’s e and ph or due to resonant dissipation from atomic defects along the SLG edges[99]). This affects the performance of both 1d and 2d contacts. We will start by assuming τC to be everywhere the same, so to derive an upper limit for the performance, then consider the effects of faster cooling at the contacts.

To systematically optimize d and EF, we continuously vary them within the range −100 nm < d < 300 nm and −0.21 eV < EF < 0.21 eV. The unbiased RI,ext is plotted in Figure for both polarizations (TE and TM) and both contact geometries (1d and 2d) for the fully embedded Si WG configuration. 1d is better than 2d in all the parameter space. RI,ext increases as d is reduced, reaching an optimum at d = 20 nm and d = 50 nm for TE and TM polarizations, respectively (see Figure c,f), where the best compromise between plasmonic field confinement and losses is achieved (see Figure and Methods). If the contact gets closer than this optimal d or overlaps with the WG (i.e., d < 0), RI,ext drops sharply due to increased metal absorption and scattering of the mode on the Au contact edge (see Methods). We note that ref (100) presented the case of complete overlap between contact and underlying WG (i.e., d < −450 nm), reporting RI,ext ∼ A/W as a result of optimistic SLG property values (i.e., heat capacity ce ∼150 J m–3 K–1 and cooling time τC ∼ 10 ps; thus interfacial heat conductance Γcool = ce/τC ∼ 5 × 103 W m–2 K–1 ∼ 10 times smaller than our ∼5 × 104 W m–2 K–1, and also zero contact resistance). Indeed, simulating the ref (100) structure using their parameters we reproduce their findings, but with our SLG property assumptions, we obtain RI,ext < 0.1 A/W, which is in line with Figure . We stress that the use of improper SLG parameters can lead to erroneously inflated responsivities, e.g, ∼ 1000 A/W in ref (101) (here τC ∼ 5 ns was used, instead of the experimentally measured τC ∼ 3 ps,[46,82−89] and zero contact resistance). For TM, the response is less sensitive to d, due to the more extended fields and stronger coupling with the Au SPPs, as evident in Figure . For both cases, the optimal EF = ±0.07 eV. This is the optimal point of two counter-acting trends: at smaller EF, s drops sharply. At larger EF, thermal conductivity and thermal capacity increase (see Methods) resulting in reduced Te gradients.

Figure 4

RI,ext [A/W] as a function of SLG EF and d for (a,b) TE and (c,d) TM modes. (a,c) 1d and (b,d) 2d contacts. Calculations are for fully embedded Si WG, with w = 450 nm and L = 30 μm.

We now consider the 1d contacts, EF = −0.07 eV, and perform optimization simulation runs, shown in Figure for both TE and TM polarizations. The effect of Si WG position with respect to the top oxide surface is shown in Figure a,b for two d. The fully embedded configuration is the optimal one for both polarizations. This is also easier to fabricate because the device is on a flat substrate. In Figure c,d, the effect of w is studied, assuming the fully embedded configuration. Different trends are observed between the two polarizations. For the optimal d = 20 and 50 nm for TE and TM, the peak RI,ext is observed at w = 350 and 450 nm, respectively. Narrowing the WG width results in vanishing RI,ext for TM, but not for TE. In both cases, detuning from the optimal w degrades RI,ext. A wider WG spreads out the mode, and a narrower WG reduces mode confinement, both cases resulting in smaller Te gradients.

Figure 5

RI,ext (A/W) for SLG EF = −0.07 eV at 1d contact configuration, as a function of (a,b) WG embedding (at L = 30 μm and w = 450 nm), (c,d) w (fully embedded Si WG and L = 30 μm), (e,f) L (fully embedded Si WG and w = 450 nm). The numbers on the curves indicate different d. Panels (a,c,e) are for TE and (b,d,f) for TM mode.

Figure e,f shows the effect of device length. The trends in TE and TM polarizations are very similar, with a monotonic RI,ext increase for longer devices. This is due to larger overall absorption and smaller SLG channel resistance. An opposite trend is observed for the external voltage responsivity RV,ext (i.e., photovoltage Vph to incoming power Pin(30)), where the higher absorption density in the device entrance promotes a larger RV,ext for shorter devices (see Methods).

The dependence of PTE response on SLG EF opens a new avenue for dynamic control of both resistance and responsivity, towards a balanced photodetection scheme.[16−19] This is an established method to reduce the effect of intrinsic light-source noise.[16] A simple embodiment is realized by two PDs of equal RI,ext, whereby subtraction of their photocurrents removes the excess noise.[16] The balanced PD pair output remains zero until a signal difference causes an “unbalance”, thus a net output.[16] Balanced PDs are also essential in coherent detection schemes.[19] which can significantly increase the transmission capacity by using the phase, amplitude, and polarization of the optical signal to carry information.

Figure a shows a schematic concept in which the Si WG is used as a gate, and a secondary gate is inserted on the side (we assume it does not affect the optical mode or the SLG absorption profile). The device has L = 30 μm, 1d contact layout, fully embedded WG, w = 450 nm, and d = 20 nm, at TE polarization. The device resistance RD as a function of WG and side SLG EF is in Figure b, while the corresponding RV,ext and RI,ext are in Figure c,d, respectively. Under these assumptions (see Methods), RD = 130 ± 50 Ω (∼ ± 40% change) as VG varies. A sixfold pattern emerges, typical of PTE,[62] with values ranging between 0 and ∼100 V/W or 0 and ∼0.9 A/W for RV,ext and RI,ext, respectively. RV,ext increases further for shorter L, as shown in Methods, where it can exceed 200 V/W.

Figure 6

(a) Schematic double-gating architecture, employing a WG gate and a side gate. (b) Resistance, (c) RV,ext [V/W], and (d) RI,ext [A/W] as a function of SLG “WG” and “side” EF, for the TE mode, d = 20 nm, L = 30 μm, w = 450 nm, 1d contact and fully embedded Si WG.

The operational optimal is at EFWG = EFside = ±0.06 eV for RV,ext, reaching up to 102 V/W, but at EFWG = ±0.06 eV, EFside = ±0.2 eV for RI,ext, reaching up to 0.88 A/W. The reason is as follows: the SLG EF above the WG (where the highest Te gradients are found) needs to be EFWG = ±0.06 eV. Increasing the side |EF| > 0.06 eV results in s reduction, as well as electrical resistance reduction (see Methods). This translates into a reduced (because of s) thermoelectric voltage (RV,ext reduction), but with a marginally increased (because of resistance) thermoelectric current (RI,ext increase). In either case, the independent variation of EFWG and EFside can enable independent dynamic control of RD, and RV,ext, towards balanced photodetection.

RV,ext and RI,ext assume open-circuit and short-circuit conditions, respectively,i.e., no power is transferred out of the system. It is instructive to extrapolate to the case of an external load RL closing the circuit with RL = RD, the condition for maximum power transfer efficiency, whose ideal value is ηmax = VPTE2/4RDPin.[102] For Pin = 1 μW, we find ηmax∼ 0.002% at RV,ext = 100 V/W and RD = 120 Ω. Within the linear regime, ηmax increases with increasing Pin. In ref (44), the linear regime extended up to Pin = 0.1 mW, beyond which the responsivity dropped as Pin–1/3 due to SLG’s nonlinear response to temperature.[76,86,103] Scaling our findings to the ref (44) trends, we get ηmax∼ 4% at Pin = 1 W. These are upper limits. Full device circuit modeling is needed for accurate evaluations.[104]

Until now, we made the simplifying assumption that Au contacts do not affect the e local cooling rate in SLG at (or under) the contacts, and assumed a fixed τC ∼ 3 ps[34,75] everywhere. However, it is expected that Au ph and e may increase locally the SLG e cooling rate.[97,98] The Au e–e and e–ph thermalization times were estimated in the 1–3 ps regime by theoretical[105,106] and experimental[107−111] works, with the smallest reported value ∼ 0.25 ps.[110] Another source of increased cooling could be related to roughness in the metal contact. For the 1d case, on the other hand, increased cooling near the contact could originate by resonant dissipation from atomic defects along the SLG edge.[99] To evaluate the effect of increased scattering, we assume a locally reduced cooling time τCred in SLG under the contact and up to a distance δ away from it (for the 1d contact τCred involves only this δ). In the absence of experimental δ values, we assume, for simplicity and without loss of generality, δ = 25 nm as used in ref (98). τCred also lacks an experimental value, so it is used here as a free parameter. Simulations with τCred reduced to 0.1 ps are shown in Figure for the fully embedded TE mode case, with SLG EF = −0.07 eV, d = 20 nm, L = 30 μm, and w = 450 nm. RI,ext drops for smaller τCred, but at a faster rate for 2d compared to 1d contacts. This trend is reversed when τCred approaches 0.1 ps. RI,ext reduces by 32% and 54% at τCred = 0.5 ps for the 1d and 2d cases, respectively. Thus, an increased e cooling rate at the contacts will impose a significant RI,ext reduction, more strongly for the 2d case, without however altering the main predictions of our work (see Methods).

Figure 7

RI,ext as a function of τCred in SLG at/under the metal contact, normalized to RI,ext when τCred = 3 ps.

We next validate our results by comparing our model findings with the measurements of two similar devices, ref (35), where 2d contacts were used, and ref (34), where 1d ones were used (both in TE polarization). Simulations are done using the experimental device geometries of refs (34) and (35) detailed in Table . In the 2d case[35] some missing information is assumed: in the experiment, there was no gate on SLG, so we assume p-doping EF = −0.14 eV.[94,112] We assume μq = 2000 cm2/Vs as for ref (45), and a unit length contact resistance ρC = 1.2 kΩ μm.[67] For the 1d case,[34] we assume μq = 7000 cm2/Vs and ρC = 0.5 k Ωμm[65] (in ref (34) μq = 1000 cm2/Vs was estimated, but with the effect of contact resistance integrated into the mobility), which, at the optimum |EF| ∼ 0.1 eV, yield RD ∼ 93 Ω, very close to the experimental value. For both contacts, we assume the same τC = 3 ps and τCred = 0.5 ps. Using the assumptions of Table , we reproduce the experimental resistance and RI,ext of refs (34) and (35). The final agreement between simulated and measured results confirms the validity of our model. A common τCred = 0.5 ps assumption is adequate for both contact designs, confirming that there is faster cooling of SLG e at the metal contact. Small discrepancies between experiments and models can be due to a variety of reasons. Thus, rather than fitting τCred to coerce an exact agreement, we adopt τCred = 0.5 ps as a reasonable assumption.

Table 1

Setup of Selected Experimental Devices (TE Polarization)[34,35] and Comparison between Measurements and Simulations

	contact type	1d[34]	2d[35]
device setup	device length L	40	30	μm
	S–D distance W	3	1.4	μm
	contact distance d	0.2	0.3	μm
	WG width w	0.52	0.4	μm
	SLG-Si spacer thickness	35	25	nm
	electron cooling time τC	3	3	ps
	carrier mobility μq	7000a	2000a	cm2/Vs
	residual local charge n0*	3b	7b	(×1011) cm–2
	graphene Fermi level EF	–0.11	–0.14a	eV
	contact resistance ρC	0.5a	1.2a	kΩ μm
measurements[34,35]	graphene absorption αSLG	40	35	%
	device resistance RD	96	187	Ω
	current responsivity RI,ext	0.078	0.007	A/W
simulations	graphene absorption aSLG	40	37	%
	device resistance RD	93	187	Ω
	current responsivity RI,ext	0.12	0.0094	A/W

Assumed based on reported SLG quality and device resistance.

Estimated by the linear relation between 1/n0* and μq according to ref (113) (see Methods).

This confirms that RI,ext ∼ 0.6 A/W is possible, for L = 30 μm with the faster τCred = 0.5 ps at the contacts. In terms of external quantum efficiency (collected e–h pairs to incoming photons ratio[30]): EQE = RI,exthc/eλ ∼ 48%. By considering the simulated SLG absorption αSLG ∼ 50% (∼ 30% transmission and ∼ 20% scattering and parasitic contact absorption losses) in our best design, we get an internal quantum efficiency (collected e–h pairs to absorbed photons ratio[30]) IQE ∼ 100%. We note that high IQE (even >100%) are a result of carrier multiplication, i.e., the creation of multiple HCs per absorbed photon.[46,76,77,81,82] HC multiplication and carrier heating is very efficient in SLG,[77] and can be exploited for various applications.[77]

To put these numbers in perspective, we derive the ideal internal PTE performance (responsivity and quantum efficiency) to set a theoretical upper limit of an asymmetric contact architecture. We make two assumptions: (a) absorption occurs only in SLG (no scattering or metal absorption) and (b) absorption occurs in a δ-distribution width at the contact edge (maximized field confinement). Assuming that ΔTe exponentially decays in both x (along the source–drain) and y (along the WG) directions, its profile is given by:where ΔTe0 is the peak Te rise, is the cooling length across the SLG channel, and ψ is the decay length due to SLG absorption along the WG length (used as a free parameter). κ and ce are the SLG heat conduction and capacity, respectively. For a long device (L ≫ ψ), all light is absorbed, and we get the ideal internal current responsivity (see Methods):while for the smallest length (L → 0) we get the ideal voltage responsivity:where g [Ω–1 m–1] is the device electrical conductance per unit length, and is a generalized heat exchange coefficient. For our SLG parameters (EF = −0.07 eV, τC = 3 ps, and μq = 10,000 cm2/Vs) for ideal (nonabsorbing) 1d contacts we find RI,int∞ ∼ 2.5 A/W (∼ 1.7 A/W if we include the 32% reduction at τCred = 0.5 ps). These correspond to ideal internal quantum efficiency IQE∞ = 200% (136% for τCred = 0.5 ps). We find that our proposed device is at ∼35% of the ideal performance (see Methods). If we include the metal absorption in the infinite device (∼28%, extrapolated from the ∼20% of the L = 30 μm device), we estimate RI,ext∞ = 0.72 A/W and RI,int∞ = 1.22 A/W for the ideal case of maximum field confinement (for τCred = 0.5 ps and ρC = 1 kΩ μm). Figure puts all our findings into perspective, plotting the validation studies and predicted performance (proposed and ideal) in one graph. The excellent agreement between simulation and experiments (blue points in Figure ) demonstrates the overall validity of our model.

Figure 8

Simulated and measured RI,ext of the devices in refs (34) and (35) (blue points). The red lines mark the highest RI,ext prediction and the theoretical ideal internal RI,int∞ for integrated asymmetric PTE PDs, including the 32% reduction at τCred = 0.5 ps.

We now consider other performance characteristics, i.e., sensitivity and speed. The sensitivity is quantified by the noise equivalent power (NEP), defined as NEP = In/RI,ext, where In is the root-mean-square noise current density per hertz of BW in A/Hz0.5.[75] At the optimal operation point with RI,ext = 0.6 A/W (assuming the faster cooling τCred = 0.5 ps at the contacts) and considering only thermal (Johnson) noise IJ (because of zero dark current) (98) (see Methods), we estimate intrinsic NEP ∼ 22 pW/Hz0.5. An interesting comparison is with the sensitivity of similar devices operated under a source–drain bias, VSD, in which case dark current enters the shot noise. E.g., assuming VSD = 0.5 V[31,45] and RD = 100 Ω, we find ID = 5 mA. Taking into consideration the shot noise component, the total noise current spectral density becomes yielding, for RI,ext = 0.6 A/W, a NEP ∼70 pW/Hz0.5 at P = 2.5 mW power consumption, more than triple the NEP of our unbiased device.

We estimated the RC time constant of the device using the cutoff frequency fc = {2πRD{[CG–1 + Cq(EF)−1]−1 + CSD}}−1, where CG is the capacitance due to local gates, Cq(EF) is the SLG quantum capacitance,[114] and CSD is the parasitic device capacitance. We assume CSD = 20 fF as estimated in ref (35) for a similar device configuration. The gate capacitance is CG = εε0A/t, where ε0 = 8.85 × 10–12 F/m is the vacuum permittivity, ε = 3.5 is the hBN static dielectric constant,[115]t = 10 nm is the hBN thickness between SLG and substrate, and A is the gated area. Cq(EF) = e2v(EF)A, where v(EF) is the SLG density of states at energy EF (see Methods). For the fully gated device (both WG and side) A = 30 × 1.1 μm2, while for a WG gate only, A = 30 × 0.35 μm2 (assuming the optimal TE configuration at L = 30 μm). For RD = 100 Ω and EF = −0.07 eV, the fully gated and WG-gated configurations yield cutoff frequencies fc ∼ 15 GHz and ∼ 34 GHz, respectively. If no gate is used, then fc can reach up to ∼ 80 GHz. We note that SLG τC ∼2–4 ps,[46,82−89] and metal HC transfer/injection and cooling times of sub-ps[116] and ps,[108,117] result in a PTE-GPD intrinsic speed limit ∼1/τC ∼ 250–500 GHz, much larger than the estimated RC device characteristic frequency (<100 GHz), making the latter a good estimate for the expected BW.[35]

Conclusions

Given the absence of band gap in SLG, an unbiased operation is preferred for GPDs to avoid large dark currents, shot noise, power consumption, and unwanted joule heating. Placing the metal contacts asymmetrically with respect to WGs promotes plasmonic-assisted light absorption in the SLG channel and allows for unbiased photodetection. Comprehensive optical-thermal-electrical modeling shows that, by tuning the SLG EF and device architecture, high responsivity (RI,ext ∼ 0.6 A/W), sensitivity (NEP ∼ 22 pW/Hz0.5), and speed (f ∼ 80 GHz) can be achieved for integrated photonics. This architecture can be further enhanced with local gates, yielding independent control over device resistance and responsivity, towards integrated balanced photodetection. Comparison with refs (34) and (35) validates our model assumptions and predictions. Together with the derived analytical expression for the ideal performance, this gives a perspective and outlook for integrated GPDs. E.g., in the ideal responsivity we assumed a fixed cooling time (τC = 3 ps), carrier mobility (μq = 10,000 cm2/Vs), and contact resistance (ρC = 1 kΩ μm). Improving them will also increase responsivity (see Methods). Target areas of focus for improving performance should then be (i) increased SLG mobility (increased RI,ext and f), (ii) longer cooling time (increased RI,ext), and (iii) lower contact resistance (increased RI,ext and f). Given our design’s losses in scattering, transmission, and parasitic contact absorption, the focus should also be on (iv) improved plasmonic and/or metamaterial contact structures (less absorption losses). These pave the way toward RI,ext > 1 A/W, NEP <10 pW/Hz0.5, and f > 100 GHz in an unbiased integrated GPD.

Methods

Optical Modeling

Optical calculations are performed with the Finite-difference time-domain method (FDTD, Lumerical[118]). The computational cell dimensions are 4 × (L + 4) × 5 μm3, with perfectly matched layer (PML) conditions in all directions and with a 5 nm grid. The light source is the fundamental TE or TM optical mode of the Si WG at λ = 1550 nm. The dimensions of the device layers are given in Figure and Table . The Au dielectric function is fitted with a Lumerical model.[119] hBN is anisotropic[120] with different permittivity in the in-plane (⊥) and out-of-plane (∥) directions. At λ = 1550 nm, its refractive index is[120]n⊥ = 2.187 and n∥ = 1.715. For SiO2 and Si, we use nSi = 3.4757[121] and nSiO2 = 1.444.[121] SLG is implemented as a 2d surface, with optical response modeled by the Kubo conductance[122] σ = σintra + σinter:where Ω = ω + iτopt–1, τopt is the scattering time, f(ε; μ, Te) = [e(ε–μ)/k + 1]−1 is the Fermi–Dirac distribution, and ∂ε ≡ ∂/∂ε. τopt is related to EF and μq as τopt = μq|EF|/evF2,[15] where vF = 106 ms–1 is the SLG Fermi velocity. For μq = 10,000 cm2/Vs and |EF| = 0.2 eV, we get τopt = 200 fs, used in eq .

Thermoelectric Modeling

We assume the quasi-cw case and solve the heat dissipation equation:[74]where κ is the electronic thermal conductivity, Π = sTe is the Peltier coefficient, q = −σs∇Te is the local thermoelectric current, σ is the electrical conductivity, ce is the electronic heat capacity, ΔT = Te – Tl, αden is the absorption density, and Pin is the incoming power. Note that in eq , −∇Π· q = q· (σ–1q) – Teq· ∇s, where the first term on the right is the Joule heating[123] and the second term includes both Peltier[124] (∇s at junction) and Thomson[125] (∇s in thermal gradient) effects. Due to the large SLG lattice heat capacity (compared to the electronic one),[90] we assume constant Tl = 300 K. The SLG parameters μ, σ, s, ce, κ, and αden are functions of EF and Te and are explicitly considered as such. The self-consistent solution of eq provides the Te distribution, from which the thermoelectric voltage is obtained:

The photocurrent is then IPTE = VPTE/RD, where RD = RG + 2RC with the SLG channel resistance and RC = ρC/L is the contact resistance, with ρC being the unit length contact resistance in units of Ω μm. Dividing by the input power, we get the external responsivities RV,ext = VPTE/Pin and RI,ext = IPTE/Pin.

Zero bias PDs are limited by the Johnson noise,[98,126,127] when operating in frequencies above the corner frequency f0 (defined as the frequency where the flicker (1/f) noise is equal to thermal or shot noise, typically ≤100 kHz for SLG devices[128]), assuming that they are perfectly shielded to minimize external noise and that have been impedance matched to minimize the amplifier noise. Also, possible contributions from generation–recombination noise, which occurs within the e–e scattering time scale (<50 fs[46,76,77]), have a small effect on SLG’s local thermal equilibrium which gives rise to the PTE response and are not considered here. Thus the noise current (root-mean-square noise current density per Hz of BW in A/Hz0.5) is ,[98] where kB is the Boltzmann constant and T is the operation temperature (300 K), and the intrinsic NEP = In/RI,ext in units of W/Hz0.5. We note that a linear photoresponse as a function of power is expected because the GPD operates in the weak heating regime (ΔT ≪ Tambient), where the electronic heat capacity can be considered constant.[34,37,76,98]

At finite Te we obtain the chemical potential from the solution of[103] ∫0∞v(ε)[f(ε; μ, Te) – f(ε; −μ, Te)]dε = EF2/πℏ2vF2, where v(ε) = 2|ε|/πℏ2vF2 is the SLG density of states at energy ε. The other SLG electrical and thermal parameters in Figure are calculated as follows: electrical conductivity σ(μ, Te) = , where σ(ε) = q[μqn(ε) + μ̅n*(ε)], with μq = μe/(μh) for ε > 0/(ε < 0) and μ̅ = (μe + μh)/2. The effective residual local charge fluctuation at energy ε is n*(ε) = , where n(ε) = ε2/πℏ2vF2 is the SLG charge density at energy ε and n0* is the residual local charge fluctuation at the charge neutrality point.[129,130] From the Mott formula,[131]. The electronic heat capacity[103], while thermal conductivity by the Wiedemann–Franz law[132] κ(μ, Te) = L0σ(μ, Te)Te, where L0 = 2.44 × 10–8 W Ω K–2 is the Lorenz number.

Figure 9

(a) Thermal conductivity, (b) specific resistivity, (c) thermal capacity, and (d) s as a function of SLG EF for e/h mobility μq = 10,000 cm2/Vs, residual local charge fluctuation n0* = 1011 cm–2, and operation temperature 300 K.

Model Assumptions

The thermoelectric calculations assume SLG with μq = 10,000 cm2/Vs[75] for both e/h, residual local charge fluctuation n0* = 1011 cm–2[75] and τC = 3 ps.[34,75] We use a typical value of unit length contact resistance ρC = 1 kΩ μm,[65,67,75] which for the 30 μm long device results in 2RC = 66.7 Ω. EF of the SLG channel varies from −0.21 to 0.21 eV. The EF pinning under the metal contacts is fixed at – 0.15 eV.[93] We introduce a narrow region extending 40 nm[34,73,98] from the contact edge into the SLG channel, within which the SLG EF linearly scales back to the assumed channel EF. For the double-gating architecture, the extension of the transition region in the contact close to the WG is bound by d. Almost identical results are obtained by assuming full electrostatic simulations, Figure . EF can be tuned by VG as EF = where εhBN = 3.5[115] is the hBN spacer relative dielectric constant, and thBN = 10 nm is its thickness. The breakdown electric field for hBN is ∼2 MV/cm for polycrystalline[115] and ∼8 MV/cm for single crystal.[133] In our case, the VG = 1.67 V required to dope SLG up to |EF| = 0.21 eV (the upper limit of our simulations) will produce an electric field ∼1.67 MV/cm, well below breakdown.

Figure 10

(a) EF spatial distribution across the SLG channel for the double-gating with “WG” EF = −0.06 eV and “side” EF = −0.21 eV. (b) Te increase distribution. The black solid lines correspond to results from the simplified EF spatial distribution presented in the main text, while the red dot lines are the results using the EF spatial distribution obtained by explicit electrostatic simulations.

Voltage Responsivity

We adopt the 1d contact configuration, EF = −0.06 eV, and perform a series of optimization simulation runs, Figure , for both TE and TM polarizations to investigate the effect of device length on RV,ext. The trends are very similar, with a monotonic RV,ext increase for shorter devices. This is due to the higher absorption density in the first μms of the device.

Figure 11

RV,ext (V/W) for SLG with EF = −0.06 eV at a 1d contact configuration, as a function of L (at fully embedded Si WG configuration and w = 450 nm). The numbers on the curves indicate different d. Panel (a) is for the TE, and panel (b) is for the TM mode.

Ideal PTE Responsivity and Quantum Efficiency

To estimate the ideal PTE internal responsivity and quantum efficiency, we assume that absorption occurs only in SLG and close to one of the contacts (e.g., at x = 0) with a fixed τC. At steady state, for x ≠ 0:orwhere is the cooling length. Assuming a decay length ψ due to absorption along the WG length L, the Te profile can be written as:where ΔTe0 is the peak Te rise, and the variables x (y) run perpendicular (along) the WG. ψ is used as a free parameter. The power lost to phonons in steady state is ceτC–1ΔTe(x,y). By integration, we find the total power Pin:

The PTE voltage is found by integration over L (in the x direction we assume W is much larger than ξ):

The voltage responsivity is then:where the term in the parenthesis accounts for light lost, that is, not absorbed, when L is comparable or smaller than ψ. By expanding ξ we find:where is a generalized heat exchange coefficient in W/mK. The max is at L → 0, where the absorbed power density, thus Te, is the highest:

To find RI, we need the resistance as the sum of the SLG channel and contact contributions RD = RG + 2RC=(ρG′+2ρC)/L, with ρG′ = ρGW, ρG is the graphene specific resistivity, and ρC the contact resistance [Ω m]. Setting the device conductance per unit length g = (ρG′ + 2ρC)−1 [Ω–1 m–1] then:RI increases as we increase the device length (voltage drops but resistance drops too). For long devices (i.e., all light is absorbed in the SLG channel) we get the ideal internal responsivity:

A comparison between R∞ and R of our proposed design is shown in Figure . The ideal internal quantum efficiency is:[30]

Figure 12

RI,int∞ and RI,ext for the double-gating architecture as a function of SLG channel EF and SLG “WG” EF, respectively (in the latter case, the “side” EF is set at EFside = −0.2 eV). In both cases, we include the 32% reduction at τCred = 0.5 ps.

Effect of Mobility, Cooling Time, and Contact Resistance on Device Performance

We adopt the 1d contact configuration and perform simulation runs for the optimum TE configuration of Figure to investigate the effect of μq, ρC, τC, and τCred on device performance. μq covers 5000–50,000 cm2/Vs, assuming a linear relation between 1/n0* and μq, according to ref (113). For τC, we use 1.5, 3, 5.5 ps, where the last value was measured in WSe2-encapsulated SLG (WSe2/SLG/WSe2 stack with 124 nm total thickness, μq ≥ 10,000 cm2/Vs).[89] As shown in Figure a, for zero contact resistance, higher μq and lower n0* result in monotonic increase of RI,ext. s saturates with improved SLG quality (i.e., for μq ≥ 10,000 cm2/Vs, n0* ≤ 0.2 × 1012 cm–2)[113,134] as the energy scale of n0* becomes comparable to kBT,[134]Figure b. These RI,ext results for ρC = 0 (channel limited) are consistent with eq , where g = (ρG′)−1 ∝ μq and , thus . When a finite ρC is introduced, the trend changes, and the peak RI,ext is observed for lower μq as ρC increases. In the limit where the total device resistance is dominated by the contact resistance g ∼ 1/2ρC (contact limited), the dominant contribution comes from the increased thermal conductivity. Thus , i.e., reduced for increasing μq.

Figure 13

(a) RI,ext as a function of μq for three ρC for the optimal TE configuration of Figure with τC = 3 ps and τCred = 0.5 ps. (b) s as a function of EF and μq. A linear relation between 1/n0* and μq is assumed as for ref (113). (c) RI,ext for EF = −0.07 eV, as a function of τC and τCred with ρC = 1 kΩ μm and μq = 10,000 cm2/Vs. All RI,ext are normalized to RI,ext when τCred = τC = 5.5 ps. (d) RI,ext for EF = −0.07 eV as a function of τC and d. All RI,ext normalized to that for τCred = τC = 3 ps and d = 20 nm. All calculations for the TE mode, L = 30 μm, w = 450 nm, 1d contact, and fully embedded Si WG.

An increased cooling time improves RI,ext. As shown in Figure c, for τCred = τC, 90% and 30% increase in RI,ext is achieved for τC = 5.5 ps compared to 1.5 and 3 ps, respectively, consistent with what is expected from our analytical theory . When we introduce faster cooling at/under the metal contact (τCred < τC), the performance differences diminish and converge to a common value. The faster cooling at/under the metal contacts does not alter the optimum device configuration. As shown in Figure d, the optimal d is unaffected by τCred.

Trade-off between Field Enhancement and Plasmonic Losses

As shown in Figures and 14, the plasmonic excitation in the metal contacts results (as we reduce d) in field redistribution, enhanced field confinement, and increase of the SLG absorption density near the metal contact.

Figure 14

Si WG (w = 450 nm) optical mode field intensity profile for (a) TE and (b) TM polarization. |Ex| field component of the hybrid optical-plasmonic mode for (c) TE (d = 20 nm) and (d) TM (d = 50 nm). The SLG absorption profile is shown as a red line in (c,d). Calculations are for 1d contact and fully embedded Si WG.

This increased absorption density is translated in larger Te and RI,ext with optimum d = 20 nm for TE and 50 nm for TM. To understand this behavior, we plot in Figure the SLG absorption and the parasitic losses (metal absorption and scattering) as a function of d for both TE and TM modes. As d decreases to its optimal value, the gain from the increased plasmonic field confinement of the hybridized optical-SPP mode dominates the parasitic losses, yielding an enhanced Te gradient and RI,ext. Below the optimal d, metal losses and scattering increase at the expense of SLG absorption, resulting in reduced RI,ext, Figure .

Figure 15

(a) SLG absorption, αSLG, and parasitic losses (metal absorption and scattering) as a function of d for (a) TE and (b) TM modes. Calculations are for w = 450 nm, L = 30 μm, fully embedded Si WG, 1d contacts.

Effect of Metal HC Injection/Transfer on Device Performance

As d reduces and the absorption in the metal contact increases due to the excitation of SPP modes (see Figure ), photoexcited HC in the metal can in principle inject[91] into the SLG channel and affect the responsivity.[92] To quantify this, we estimate an upper limit of the metal HC contribution to the photocurrent using the optimized device (TE polarization, d = 20 nm) where we find a metal absorption αM ∼ 20% (see Figure a). If we assume all metal HCs with velocity normal to the interface to be injected and contribute to the photocurrent (i.e., 1/4 of them), then the metal HC current contribution is RI,HC = αM × 0.25 × e/ℏω = 0.0625 A/W. This corresponds to ∼ 10% of the maximum calculated RI,ext = 0.6 A/W. Given this upper limit, we expect the metal plasmonic HC effects to be a small correction.