| Literature DB >> 27819264 |
Jaewoo Shim1, Seyong Oh1, Dong-Ho Kang1, Seo-Hyeon Jo1, Muhammad Hasnain Ali1, Woo-Young Choi1, Keun Heo2, Jaeho Jeon3, Sungjoo Lee3, Minwoo Kim3, Young Jae Song3, Jin-Hong Park1.
Abstract
Recently, negative differential resistance devices have attracted considerable attention due to their folded current-voltage characteristic, which presents multiple threshold voltage values. Because of this remarkable property, studies associated with the negative differential resistance devices have been explored for realizing multi-valued logic applications. Here we demonstrate a negative differential resistance device based on a phosphorene/rhenium disulfide (BP/ReS2) heterojunction that is formed by type-III broken-gap band alignment, showing high peak-to-valley current ratio values of 4.2 and 6.9 at room temperature and 180 K, respectively. Also, the carrier transport mechanism of the BP/ReS2 negative differential resistance device is investigated in detail by analysing the tunnelling and diffusion currents at various temperatures with the proposed analytic negative differential resistance device model. Finally, we demonstrate a ternary inverter as a multi-valued logic application. This study of a two-dimensional material heterojunction is a step forward toward future multi-valued logic device research.Entities:
Year: 2016 PMID: 27819264 PMCID: PMC5103069 DOI: 10.1038/ncomms13413
Source DB: PubMed Journal: Nat Commun ISSN: 2041-1723 Impact factor: 14.919
Figure 1BP/ReS2 heterostructure.
(a) Schematic illustration of the BP/ReS2 heterostructure on SiO2/Si substrate. (b) AFM (atomic force microscope) image of the BP/ReS2 heterostructure sample. (c) Thicknesses of the BP (top) and the ReS2 flakes (bottom) corresponding to the yellow lines marked in b. (d) Raman spectra of the ReS2, BP/ReS2 overlapped and BP regions. (e) Three-dimensional KPFM mapping image of the BP/ReS2 heterostructure (top) and histogram distributions of ΔVCPD extracted from the KPFM mapping image (bottom). (f) Work function values of BP and ReS2 films. The inset shows schematic illustration of the KPFM measurement system. (g,h) Energy band alignments of BP and ReS2 heterojunction at equilibrium (g) before and (h) after contact. EC, EF and EV are the lowest energy level of the conduction band, the Fermi level and the highest energy level of the valence band of the semiconductors, respectively.
Figure 2Electrical characteristics of BP/ReS2 heterojunction-based NDR device at room temperature.
(a) An illustration of the BP/ReS2 heterojunction NDR device. (b) Current–voltage (I–V) characteristic of the BP/ReS2 NDR device on a linear scale. The inset shows the PVCR values for the three different BP/ReS2 NDR devices. (c) Experimentally measured and theoretically calculated I–V curves of the BP/ReS2 NDR device on a log scale. (d) Energy band alignment of the BP/ReS2 heterojunction under various bias conditions. Width of the red arrow presents the magnitude of the current. (e) Extracted peak- and valley-current values of the BP/ReS2 NDR device in eight consecutive I–V sweeps. (f) Drain current–drain voltage (ID–VD) curves under various gate biases from 30 V to −30 V. (g) PVCR values of the BP/ReS2 NDR device as a function of gate voltage.
Figure 3Temperature-dependent electrical characteristics of BP/ReS2 NDR device.
(a) I–V curves of the BP/ReS2 NDR device at various temperatures between 180 K and 300 K. (b) PVCR values of the BP/ReS2 NDR device as a function of temperature. (c–e) Peak-current (c), valley-current (d), valley- and peak-voltage values of the BP/ReS2 NDR device as a function of temperature (e), which were extracted from the experimentally measured and the theoretically calculated I–V characteristic curves. The inset in c shows the probability of states being occupied (f(E)) as a function of given energy E relative to EF(E−EF). The inset in d shows the theoretically calculated diffusion current of the BP/ReS2 NDR device at various temperatures.
Figure 4Ternary inverter with three logical states.
(a) Schematic illustration of the ternary inverter. (b) Equivalent circuit configuration of the ternary inverter. (c) Optical image of the ternary inverter. (d) VIN versus VOUT characteristic of the ternary inverter. The inset shows an input–output table of the ternary inverter. (e,f) Load-line analysis of the ternary inverter circuit under three bias conditions: (e) 5 V