| Literature DB >> 23584123 |
Mohammadreza Dadkhah1, M Jamal Deen, Shahram Shirani.
Abstract
The compressive sensing (CS) paradigm uses simultaneous sensing and compression to provide an efficient image acquisition technique. The main advantages of the CS method include high resolution imaging using low resolution sensor arrays and faster image acquisition. Since the imaging philosophy in CS imagers is different from conventional imaging systems, new physical structures have been developed for cameras that use the CS technique. In this paper, a review of different hardware implementations of CS encoding in optical and electrical domains is presented. Considering the recent advances in CMOS (complementary metal-oxide-semiconductor) technologies and the feasibility of performing on-chip signal processing, important practical issues in the implementation of CS in CMOS sensors are emphasized. In addition, the CS coding for video capture is discussed.Entities:
Year: 2013 PMID: 23584123 PMCID: PMC3673121 DOI: 10.3390/s130404961
Source DB: PubMed Journal: Sensors (Basel) ISSN: 1424-8220 Impact factor: 3.576
Figure 1.General schematic of single-pixel camera set-up (adapted from [41]) (DMD: digital micro-mirror device; ADC: analog-to-digital converter, DSP: digital signal processor).
Figure 2.(a) Schematic of single dispersive spectral imaging system (adapted from [49]); (b) Optical set-up for random-mask image acquisition (adapted from [51]).
Figure 3.Block diagram for the digital implementation of CS coding.
Figure 4.Block diagram for the analog implementation of CS coding.
Figure 5.Block diagram of a CS encoding implementation.
Figure 6.General schematic representation of the separable-transform imager (adapted from [64]).
Figure 7.(a) Connections of each block toward the linear feedback shift register (LFSR); (b) Block connections for block-by-block read-out; (c) Block connections for column-of-blocks connections (adapted from [63]).
Summary of various CS-CMOS imagers available in the literature.
| [ | DPS | -- | -- | 1 transistor, 2 inverters, 1 AND, 1 comparator | Digital domain, Random selection after integration |
| [ | APS | 0.15 μm | 256 × 256 | 4 transistors | Analog-to-digital conversion level, Random selection after integration |
| [ | APS | 0.18 μm | 256 × 256 | 3 transistors, 3 NAND, 1 D-flip flop | Analog domain, In-pixel random selection, Differential current & Trans-impedance amplifier |
| [ | APS | 0.13 μm | 16 × 16 | 3 transistors | Analog domain, Block random selection, Switched capacitor (SC) circuits |
| [ | PPS | 0.35 μm | 256 × 256 | 2 transistors | Analog domain, Column-row random selection Differential current & Vector matrix multiplier |
| [ | APS | 0.5 μm | 128 × 128 | 4 transistors, 1 capacitor | Analog domain, Column-row random selection SC circuits |
| [ | PPS | -- | -- | 1 transistor, 1 flip flop | Analog & digital domain, In-pixel & column-row random selection |
Figure 8.Timing diagram for frame-by-frame video coding using consecutive image coding steps.
Figure 9.(a) Multiple-capture and one read-out timing diagram; (b) Cube of data for n frames.