How Materials and Device Factors Determine the Performance: A Unified Solution for Transistors with Nontrivial Gates and Transistor-Diode Hybrid Integration.

Advanced field-effect transistors (FETs) with nontrivial gates (e.g., offset-gates, mid-gates, split-gates, or multi-gates) or hybrid integrations (e.g., with diodes, photodetectors, or field-emitters) have been extensively developed in pursuit for the "More-than-Moore" demand. But understanding their conduction mechanisms and predicting current-voltage relations is rather difficult due to countless combinations of materials and device factors. Here, it is shown that they could be understood within the same physical picture, i.e., charge transport from gated to nongated semiconductors. One proposes an indicator based on material and device factors for characterizing the transport and derives a unified and simplified solution for describing the current-voltage relations, current saturation, channel potentials, and drift field. It is verified by simulations and experiments of different types of devices with varied materials and device factors, employing organic, oxide, nanomaterial semiconductors in transistors or hybrid integrations. The concise and unified solution provides general rules for quick understanding and designing of these complex, innovative devices.

Introduction

Field‐effect transistors (FETs) or thin‐film transistors (TFTs) with non‐trivial gate structures have been explored for superior functions in cutting‐edge research, including the offset‐gate structure, mid‐gate structure, split‐gate structure, light‐emitting transistors, or other multigate or partial‐gate structures.[ , , ] A significant feature is that gated and nongated semiconductor channels are coupled together. Such coupled channels are also critical to integrate sensing, memory, computing, or illumination by integrating transistors with photodiodes (PDs),[ ] light‐emitting diodes (LEDs),[ ] field emitters,[ ] sensors,[ ] and etc. Some of them are illustrated in Figure  , which are made with a broad range of new semiconductors including organic small molecules or polymers, metal oxide, low dimensional semiconductors, perovskites, and etc.[ , , , ] However, the countless possibilities of material combination and interface make it difficult to understand the relationship between material and device parameters and device characteristics. So far, these devices have been comprehended or explained case by case in experiments only through complex and special models and nonuniversal numerical simulation.[ , , ] Therefore, a concise physical picture and a general framework for understanding such new devices or predicting their characteristics are still blank.

Figure 1

From devices to transport in materials. a) Transistors and integration containing coupled channels. The lateral structures are on the first row and the vertical structures are in the lower row. b) The key physical process, i.e., charges from gated to non‐gated semiconductors. Potentials, current, length, and thickness parameters are marked. c) Transport mechanisms in materials. The single‐line arrows and double‐line arrows indicate the transport in the gated and nongated semiconductors, respectively. In (c), the yellow and grey dots represent the movable and trapped carriers, respectively, and the number of them illustrates the density in the x‐direction.

A general physical framework would answer both fundamental and practical questions: Why and what material or device factors will affect the charge transport and current conduction mechanisms? How do these factors determine the current–voltage relations and the current saturation? How is the electric potential and field distributed in the channels? How to design the device structures? The framework should also be as concise and universal as possible, so that it can be applied to devices and semiconductors with various particularities. The target of this study is to understand the mechanisms and predict the performance of those new devices made of various materials.

Here, we focus on the key physical process, i.e., charge carriers drift from the gated‐channel into a nongated channel (Figure 1b). First, we derive a basic theory framework with simple and universal equations for describing how charge transport occurs, how current–voltage relations behave, and how the electric potential and field evolve. Then, we verify the theory framework by simulating an offset‐gate transistor as an example. Finally, we apply it to examine different experimental devices and briefly discuss how to quickly understand, calculate, analyze, and design these devices.

The Physical Picture

From Gauss law and continuity principle, the current on the boundary between the gated and nongated semiconductor is continuous (Figure 1b, the gray boundary). In gated semiconductors, the electric resistance (R) is related to the drain current (I D) by using the gradual channel approximation:[ ] dV  = I D dR  = I Ddx/WμC i[V G − V th − V(x)] . Here, W is the channel width, C i is the capacitance per unit area for the insulating dielectric layer, V G is the gate voltage, V th is the threshold voltage, and V(x) is the local potential. Denote V S as the source potential as transistors with organic or low‐dimensional semiconductors usually have injection barriers, unlike silicon MOSFETs. Denote V 1 as the potential at the end (|V S|< |V 1| ≤ |V G ‐ V th|) and L as the gated channel length. Integrate dV from V S to V 1 and dx from 0 to L and we have the I–V relation above the threshold: Here, V 1 would not exceed the saturation voltage V D,SAT, which is usually above V D,SAT = V G – V th of conventional MOSFETs due to the transport in the various non‐gated semiconductors as discussed below.

In nongated semiconductors, the conduction mechanisms include: a) Fowler–Nordheim (F–N) tunneling via quantum mechanical tunneling or Poole–Frenkel (P–F) emission that occurs with rich structural defects;[ , ] b) Ohmic current or space charge limited current (SCLC) achieved by band‐conduction or thermally activated transport among localized states (e.g., at grain boundaries);[ ] c) ballistic transport without scattering (e.g., in nanotubes).[ ] Among them, Ohmic current and SCLC are mainly dominant at high current density in various semiconductors.[ , ] At the beginning of the non‐gated channel, the current density J depends on the local carrier density n and drift electric field ε:

The subscript “0” and “Sp” refer to the free carriers at thermal equilibrium and the rest carriers forming space charge regions, respectively; q is the elementary charge; η is the space‐charge‐to‐equilibrium‐carrier ratio: η  = n Sp/n 0  (Figure 1b). The n Sp responsible for forming space charge regions will increase when increasing the dielectric relaxation time τ R within which carriers are relaxed toward a uniform distribution, decreasing the carrier transit time τ T within which carriers are swept out, or increasing the injected carrier density n inj. Thus, the average η is characterized by (see Note S1, Supporting Information for details): Here, τ T ≈ d 2/(μ 2ΔV) with ΔV  = V 2  − V 1, τ R = ε sc/(n 0 qμ 2); ε sc, d, S are the permittivity, length, and current area of the nongated semiconductor; V 1 is the potential at the end of the gated‐channel (with the upper limit V G ‐ V th or V D); µ 1 and µ 2 are the carrier mobility in the gated and nongated semiconductors.

The impacts of materials and device factors on η are summarized in Equation (3). The η is also an indicator for how severe the charges injected from the gated semiconductors are limited by the transport in the nongated semiconductors: a) with weak injection and fast relaxation (η ≪ 1), most injected carriers have been relaxed, giving uniform resistivity closed to Ohmic conduction (Figure 1c‐I); b) with strong injection and slow relaxation (η ≫ 1), most injected carriers kept unrelaxed, giving the non‐uniform resistivity closed to SCLC (Figure 1c‐III); c) with the intermediate degree of injection, the conduction is in the intermediate case (Figure 1c‐II); d) when the density of trap states n t is comparable with that of mobile carriers, trap‐limited SCLC (or “trap‐fill limited,” TFL) dominates (Figure 1c‐IV). When estimating the average η, V 1 ≈ (V G − V th)/2 could be used. As η widely varies, a universal expression of the current density J is needed.

We simply assume J  =  n(n/n t0) qμ 0 ε(ε/ε t0) =An qμ 0 ε , where μ 0 is a characteristic mobility, δ − 1 and κ − 1 characterize the carrier‐density(n)‐dependent and field(ε)‐dependent mobility,[ , ] n t0 and ε t0 are the characteristic trap density and electric field, and A is a constant. In particular, δ  = T c/T  if density of trap states is in exponential distribution with energy and T c is the characteristic temperature (T c > T).[ , ] The general trap‐fill limited (TFL) SCLC for disordered semiconductors is (see Note S2, Supporting Information): where A′  =  Aδ (2δ + κ) /(δ + κ)2, α  =  δ + κ, and β  =  2δ + κ. The power‐law J–V curves have been verified in many organic or compound semiconductor diodes.[ ] In on‐state transistors or diodes, the n‐dependence of μ is mainly considered as compared with ε‐dependence,[ , , ] therefore giving κ ≈ 1 and β ≈ 2α − 1. With few defects, δ  =  κ  =  1 and Equation (4a) returns to the classic SCLC (α = 2); with rich defects, the mobility is carrier‐density dependent: μ∝n μ 0 (α > 2). In particular, α  = T c/T  + 1 when the density of defects per unit energy is exponentially distributed (with the width T C) in organic semiconductors.[ , ] For generality, Equation (4a) is rewritten into: Here, α is referred as the charge transport factor and Q 0 is referred as the charge density factor. The denominator 1 V and numerator 1 cm are introduced to keep the unit of Q 0 as C cm‐3 (the same as qn) and so the term [Q 0(ΔV/1) (1/d) ] could be regarded as the equivalent charge density in the form of Ohmic law. A larger Q 0 signifies the larger charge density if with the same α. Within a certain operational window, α and Q 0 could be regarded as independent of the voltage drop ΔV. As shown in Table  , different conduction mechanisms could all be covered by Equation (4) (usually with β  =  2α − 1) as a general expression.

Table 1

Typical current density for nongated semiconductors.The mechanisms include Ohmic, SCLC, and some other cases (vacuum diode, emission, and tunneling). The values of α, β, Q 0 are presented, where K and V a are constants. The power factors α for emission and tunneling are derived in Note S3 (Supporting Information)

Conduction mechanism	Current density	α	β	Q 0
Ohmic conduction	J=n_0qμVd (Ohm's law; when η ≪ 1)	1	1	n 0 q
SCLC	J=98ε_scμV^2d^3 [ 25 ] (Mott–Gurney law; when η ≫ 1)	2	3	98ε_sc
Trap‐limited SCLC (n‐dependent µ)	J=A^′εscδq^δ−1μ_0V^δ+1d^2δ+1 [ 22 ] [Equation 4; when η ≫ 1]	δ + 1 > 2	2δ + 1	A^′εscδq^δ−1
Trap‐limited SCLC (n‐ and ε‐dependent‐µ)	J=A^′εscδq^δ−1μ_0V^δ+κd^2δ+κ [Equation 4; when η ≫ 1]	δ + κ > 2	2δ + κ	A^′εscδq^δ−1
Vacuum diode or ballistic SCLC	J=49ε_sc2qmV^32d^2 [ 18 , 25 ] (Child–Langmuir law)	1.5	2	49ε_sc2qm
Emission (P–F and etc.)	J∼Vexp(KV) [ 25 ]	≈2	–	–
Tunneling (F–N and etc.)	J∼V^2exp(−V_a/V) [ 25 ]	≈2	–	–

The Device Performance

Current–Voltage Relations

How materials and device factors affect conduction mechanisms could be understood by combining Equations. (3) and (4). For example, the transport factor α is very sensitive to n 0 as and, thus, if the semiconductor become rich in carrier‐generating states (η ≪ 1), the SCLC‐to‐Ohmic transition could occur (α decreases from 2 toward 1). Conversely, if the injection from the gated channel (C i V G) significantly increases or the nongated channel becomes rich in trapping states (η ≫ 1), the Ohmic‐to‐SCLC transition may occur or even to the trap‐limited SCLC (α increases from 1 toward 2 and beyond).

Taking a drain‐offset transistor, or similarly a transistor‐diode hybrid integration, as an example (Figure 1b with V 2 = V D), the gated and nongated channel (Equations 1 and 4) are coupled and mutually limit each other: Here, C i = ε ox/t ox with ε ox as permittivity and t ox as the thickness of the insulating layer below or above the gated semiconductor, and V 0 is the onset voltage for the nongated channel (due to injection barriers or trap states). In the following, V 0 is omitted for simplicity and could be included by replacing V D with V D‐V 0 whenever needed. For a drain‐offset transistor, S  =  Wt sc with t sc as the thickness of the nongated semiconductor. By defining the partial voltage coefficient γ  = (LSQ 0 μ 2)/(Wd C 1)  and assuming a small contact effect (V S ≪ V 1), Equation (5) becomes its voltage form:

As V 1 < V D, the second‐order Taylor series is applied to the right and the accurate and approximated solutions are: where , , and (Note S4, Supporting Information). The accurate solution is used below and the approximated solution is for very small γ (e.g., when the nongated channel is with low conductance).

The I–V relations described by Equations (5 and 7) with V S ≈ 0 are qualitatively illustrated in Figure  . In output characteristics (Figure 2a), |I D| increases with |V ‐ V 1 ‐ V 0| (approximately with |V D ‐ V 0| as often |V 1| ≪ |V D|) until V D reaches the saturated voltage V D,SAT, beyond which the current saturates due to pinch‐off. In transfer characteristics (Figure 2b), |I D| increases with (V G ‐ V th)2 until |V D,SAT|>|V D|, beyond which the current is limited by the nongated channel. When the nongated channel has high conductance (large γ), the device behaves like a regular transistor; otherwise, the current is limited by the nongated channels (small γ) in the case of Ohmic current, SCLC, or trap‐limited SCLC. Conduction mechanisms could change if changing materials or device factors according to Equation (3).

Figure 2

Impacts of transport on I–V characteristics (qualitative). a) Output and b) transfer characteristics according to Equation (5). The trap‐limited (or TFL) SCLC is denoted as “Trap‐SCLC” (the same below). The small arrows indicate the positions where V D exceeds V D,SAT in (a) or V D,SAT exceeds V D in (b). The gray arrows point to the direction in which η increases and that the device current is increasingly limited by the nongated semiconductors.

The impacts of material and device factors on the ratio η, charge transport factor α, and charge density factor Q 0 are summarized in Figure  . The original data are given in Figure S1 (Supporting Information). As an example, the impacts of donor‐like and acceptor‐like states on I–V characteristics are shown in Figure 3b–h, including the 2D‐TCAD simulation (dots) and the fitting using Equations. (5 and 7) (curves). The 2D‐TCAD simulations were performed by solving Poisson equations and continuity formulas in fine grids and parameters are shown in Table S1 (Supporting Information). For donor‐like states, the peak energy is fixed below the conduction band edge (CB, or lowest unoccupied molecular orbit LUMO) with the same characteristic width (w D), while the maximum number of the Gaussian‐distribution (N D) is varied (Figure 3b). For acceptor‐like states, the maximum of the exponentially distributed acceptor‐like tail states (N A) is fixed as 1018 cm–3, while the characteristic width (w A) is varied (Figure 3b). With more donor‐like states, e.g., increasing n 0 = 1015 cm–3 to n 0 = 1016 cm–3, the estimated ratio η by Equation (3) sharply decreases from 151 to 1.5 (using V 1 = V G/2 = 1.5 V), suggesting that α would change from 2 toward 1. Consistently, the transport factor α decreases from 2 to 1 as N D increases, as shown in Figure 3c,d. By contrary, α increases beyond 2 as the DOS of acceptor‐like states broadens (w A increases). The evolution of output and transfer characteristics (Figure 3e–h) could all be understood by that: when N D increases, Q 0 (and thus γ) increases, leading to the increased V 1 (and thus I D) and decreased V D,SAT; the opposite occurs when w A increases. Using Equation (5) with a single set of Q 0 and α provides good fitting to both I D and V 1 simultaneously for all the cases (Figure 3e–h), validating the simplified physical picture.

Figure 3

Impacts of materials on I–V characteristics (quantitative). a) A summary of the impacts of materials and device factors on the indicator η, the transport factor α, and charge density factor Q 0. The grey arrow indicates the direction that η increases, if N A, ε sc, ε ox, V G, or V D increases and N D, n 0, S, t ox, L, or d decreases. Here, N A and N D represent the characteristic density of donor‐ and acceptor‐like states. b) Schemes of density of states (DOS) of acceptor‐rich material and donor‐rich material. c) I D–V D curves in the semilog scale. d) Extracted α  =  ∂lnI D/∂lnV D. e,f) I D–V D curves in the linear scale (V G = 3 V) and the corresponding V 1 read from a point near the end of the gated channel (7.95 out of 8 µm), which gets almost saturated when V D > V D,SAT. g,h) I D–V G curves (V D = 200 V) and the corresponding V 1, which starts decaying when V D,SAT > V D. The TCAD simulated data are drawn in dots and fitting by using Equations 5 and 7 are drawn in curves. In (d–h), results of a regular TFT are shown for references. The dotted (or dashed) arrows represent the direction that acceptor‐like (or donor‐like) states increase.

Potential and Field Evolution

The evolution of local channel potential V(x) can be derived from Equation. (5): where θ is defined as the saturation degree, θ  = 2V 1(V G − V th − V 1/2)/(V G − V th)2 , and 0 < θ ≤ 1. It quantifies the impacts of drain and gate voltages on the operational regime: when θ ≪ 1 or θ = 1, the gated channel is in the linear or saturated regime, respectively. In general, distributions of V(x) are characterized by θ and α (illustrated in Figure  ) and will change when voltages or material properties significantly change.

Figure 4

Impacts of materials on channel potential (black) and drift field (blue). a) A scheme of potential distribution. The gated channel is from X = 1 to 9 µm, the nongated channel is from X = 9 to 11 µm, and V G = 3 V. The source potential V S is referred to as zero. The gated channel changes from the saturated (b,c, V D = 85 V) to unsaturated (d,e, V D = 55 V). With V D = 55 V, the nongated channel changes from the SCLC (d,e, intrinsic semiconductor) to Ohmic conduction in donor‐rich materials (f,g, with N D = 5 ×  1017 cm–3 eV–1 and w D = 0.1 eV), or to trap‐limited SCLC in acceptor‐rich materials (h,i, with N A = 1018 cm–3 eV–1 and w A = 0.1 eV). Curves are the calculation by Equation (8) and well fit the TCAD simulation (dots). The saturation degree θ (from calculated) characterizing the gated channels and the charge transport factor α (for fitting) characterizing the non‐gated channels are shown.

The impacts of voltage scanning are exemplified in Figure 4b,c for a saturated, gated channel and in Figure 4d,e for an unsaturated, gated channel with the reasons for the transition (i.e., changing V D or V G). The impacts of materials are exemplified in Figure 4f,g by inducing donor‐like states with Ohmic conduction (α ≈ 1) in the nongated channel and in Figure 4h,i by inducing acceptor‐like states with trap‐limited SCLC (α >2), respectively. At the meantime, the gated channel also changes to the saturated regime (Figure 4f, θ  =  1) or the linear regime (Figure 4h, θ ≪ 1) due to the increased or decreased partial voltage coefficient γ (and thus V 1), respectively. For all the cases, the calculations by Equation (8) (curves) agree well with the 2D TCAD simulation (dots). Also, we could obtain the drift electric field by E (x) =   − dV/dx, Joule heating power density by p (x) = |JE| , velocity of carriers (including hot carriers) by v (x) =  μE, and carrier density by n (x) = J/(qμE)  by using Equations (5 and 8) or probing V(x) in experiments for partially gated or even regular transistors.

Current Saturation

Current saturation occurs when carrier concentration becomes depleted near the end of the gated channel, with V 1 reaching (V G ‐ V th) and V D reaching V D,SAT. As V D,SAT is the turning point in I–V curves (Figure 2) and critical for stabilizing current and tolerating signal fluctuations, it is derived from Equation (7): Here, ε ox and t ox are the permittivity and thickness of the dielectric layer and S = Wt sc. The approximate equal sign holds when γ is small or, instead, V D,SAT approaches the classic (V G ‐ V th) when γ is large. Accordingly, V D,SAT increases linearly with (V G ‐ V th)2 or (V G ‐ V th) with ideal Ohmic conduction or SCLC, respectively. We use a trap‐free semiconductor in simulations to examine V D,SAT of devices with varied parameters (V D, t ox, d, and L, Figure  ), which fall in the same line calculated by Equation (9) with α = 2 (SCLC regime, Figure 5b and Figure S2, Supporting Information). The materials or device factors that lead to increased V D,SAT are also indicated by the gray arrow.

Figure 5

Impacts of materials and device factors on current saturation. a) For drain‐offset transistors, output curves with various V G (top), t ox (middle), L and d (bottom). V D,SAT is illustrated by arrows. b) The extracted V D,SAT (dots) are compared with the calculated results from Equation (9) with α = 2 (the line). The arrow indicates that V D,SAT will increase if t ox, L, or Q 0 decreases and d, V G, or ε ox increases. c) For regular transistors, extracted ΔL of devices with various λ by changing t ox or t sc (dashed ovals). ΔL is the distance from the drain to the pinch‐off point, where the interfacial potential reaches V G – V th. Here, V D ranges from 7.5 to 20 V with the step of 2.5 V. The arrow indicates that ΔL will decrease if t sc, t ox, ε sc, L or V D decreases and ε ox or V G increases.

Interestingly, the method helps to answer another long‐standing problem: how to estimate the drain depletion‐region length (ΔL, Figure 5c) in a saturated TFT? As this region is depleted (n inj/n 0 ≫ 1) and narrow (τ R/τ T ≫ 1), ΔL could be estimated by using Equation (5) with V 1 = V G ‐ V th, V 2 = V D, d = ΔL and the SCLC limit: where is the natural length.[ ] The ΔL in accumulation‐mode, thin‐film based transistors is predicted to increase with Lλ 2, different from conventional inversion‐mode, pn‐junction based MOSFETs.[ ] This is consistent with the extracted ΔL by varying t sc or t ox in TCAD simulation (Figure 5c and Figure S3, Supporting Information). The undesired channel length modulation[ ] characterized by L/(L − ΔL) would be intensified in short‐channel TFTs, but could be weakened by decreasing λ (Note S5, Supporting Information). It also quantifies the advantages of using ultra‐thin semiconducting films in short‐channel FETs in terms of weakening the channel modulation.

Various Applications

Applications with Various Semiconductors

When using organic semiconductors in transistors or transistor–diode integrations,[ ] charge carriers are generally intrinsically low (n 0 < 1018 cm–3) and thus usually with η ≫ 1 and α ≈ 2. But charge transport of polarons could be limited by structural disorders so that it takes the forms of trap‐and‐release, variable range hopping, charge transfer, nuclei tunneling, and etc.[ ] The macroscopic conductance as a function of temperature and gate‐field could be described by the thermal activation of carriers near the exponentially distributed tail states.[ , ] In these cases, α  = T c/T  + 1 > 2 is expected, especially in a disordered film with localized tail states or trapping states.[ , , ] We have shown that various transport mechanisms of organic semiconductors could be universally described by the generalized Einstein relation,[ , ] so that the gate‐ and temperature‐dependent mobility of organic semiconductors could be included in the current framework. In addition, organic FETs usually suffer from significant contact injection barriers that lower the on‐current and cut‐off frequencies[ , ] and, thus, the contact potential V S should be considered.

When using metal‐oxide semiconductors as the nongated channels, the carrier density and field‐dependent transport mechanisms include the trap‐limited conduction, variable range hopping, and percolation.[ ] As the intrinsic carrier concentration is also usually low with abundant defects,[ ] η ≫ 1, α > 2, and a small value of Q 0 close to or below the SCLC limit would be expected. In contrast, when using semiconductors with high carrier densities as the nongated channels for light‐emitting or detecting, e.g., perovskites and 2D narrow‐bandgap materials, we expect η ≪ 1, α  ≈  1, and Q 0 ≈ qn 0. The mentioned materials will be studied in various devices in the following section.

Applications in Various Transistors and Hybrid Integration

As the first example, transistors in the drain‐offset structure have been used to stabilize current[ ] or to make high‐voltage TFTs[ ] for driving field‐emitters, piezoelectric actuators, or integrated MEMS.[ , ] Drain‐offset transistors were fabricated based on amorphous N2‐doped InGaZnO4 semiconductor (t sc = 60 nm), which is chosen for its relatively large bandgap (≈3 eV) and low intrinsic carrier concentrations[ ] to investigate the current limitation from the nongated channels. The methods of fabrications and measurements are the same as described elsewhere.[ ] The electrodes are Mo (L = 200 µm, d = 100 µm, and W = 40 µm) and the dielectric layer is SiO2 (t ox = 300 nm). The measured output characteristics are shown in Figure  , with the dots and curves representing the experimental data and fitting, respectively. The estimated η as an indicator is about 192 due to low carrier density in the N2‐doped InGaZnO4 (n 0 ≈ 1015 cm–3, V G = 30 V). The fitting results are calculated by the total resistance R tot with the channel resistance (R CH) and a back‐channel resistance (R BACK) in parallel. R CH is calculated by Equations (5 and 7) using the same parameter α (with β = 2α‐1) and a fitting parameter Q 0, while R BACK is extracted by R BACK = ∂V D/∂I D  beyond V D,SAT. The simple fittings agree well with the experimental data with α = 2.3 (trap‐limited SCLC), corresponding well with the disordered transport in amorphous InGaZnO4. The values of V D,SAT increase almost linearly with the V G (Figure 6, top) and this is also consistent with the above theories. The charge density factor Q 0 changes slightly when varying V G (Figure 6, bottom). Thus, the drain‐offset, high‐voltage TFTs could be understood by the above physical framework.

Figure 6

Various transistors and device integrations. a) A schematic representation and an optical picture of an drain‐offset TFT. b,c) Output characteristics in the linear scale or semi‐log scale. The dots are experimental data and the curves are the fitting results by using Equations (5 and 7). d) Values of extracted V D,SAT (top) and Q 0 (bottom) are shown as a function of V G. e) A schematic representation and an optical picture of the transistor–photodiode hybrid integration. The perovskite‐organic layers are denoted as “PSK & Org.” f,g) Transfer characteristics (V D = 0.1 V) in the linear or semi‐log scale. h) Light‐to‐dark current ratio (top) and the charge density factor Q 0 for the fitting (bottom) as a function of illumination power. i) A schematic representation of the MoS2 transistor integrated with OLED. j) Calculated output characteristics using the parameters in the reference[ ] with the ideal SCLC, which agrees well with the reported data.[ ] k) A schematic representation of the Si‐FET and ZnO–nanowire–emitter hybrid integration. l) Field‐emission I–V A curves. The dots are experimental data and the curves are the calculation or fitting by using Equations (5 and 7).

Transistor hybrid integration, e.g., with photo‐diodes, light‐emitting diodes, field emitters, or others for various functions, could also be effectively simplified by the above approach. As the first example, the transistor‐photodiode integration was fabricated by integrating a vacuum‐deposited InGaZnO4 TFT and solution‐processed a vertical photodiode based on perovskite‐organics [ITO‐SnO2‐(FASnI3)0.6(MAPbI3)0.4‐poly(3‐hexylthiophene)‐Au, Figure 6e]. The perovskite semiconductor is chosen as a representative, light‐sensitive semiconductor with relatively high carrier concentrations and Ohmic conduction in a diode structure.[ , ] The methods of fabrication and measurement are the same as described elsewhere.[ ] The parameters for experimental devices are: W = 1600 µm, L = 40 µm, d = 0.5 µm, t sc = 60 nm, t ox = 300 nm (SiO2), and V d = 0.1 V. Due to the high carrier density in perovskite semiconductors, the photodiodes exhibit Ohmic conduction behaviors in J–V characteristics[ ] so that η ≪ 1 and α = 1 is used here. The transfer curves are shown in the linear or semilog scale with the fitting curves (Figure 6f,g). The mobility parameters are set the same for all the curves with different illuminations, whereas fitting parameters Q 0 are varied for each illumination power and show the same trend with the light‐to‐dark current ratio (Figure 6h). These results are consistent with the above discussions and verify that Q 0 reflects the photogenerated carrier density in the non‐gated channels (photodiodes). As the second example, the performance of MoS2‐TFT and OLED integration (Figure 6i) is predicted by using Equations (5 and 7) with the device and material parameters as reported in reference[ ] and with the ideal SCLC, giving the results (α = 2, Figure 6j) close to the experimental data reported in reference.[ ] The 2D semiconductors are the extensively studied candidates for ultra‐thin, fast logic devices.[ ] As the third example, Si‐FET and ZnO–nanowire–emitter integration (Figure 6k) were fabricated as described elsewhere[ ] and the I–V characteristics are shown in Figure 6l. The nanowire emitter is studied here as it could be used in the source of fast electron beams for microscope or nanolithography technologies.[ ] The I–V characteristics could be fitted by using Equations (5 and 7) with α = 2.1, supporting that the field‐emission by F–N tunneling into vacuum at large anode bias V A could also be approximated by Equation (5). These results confirm the proposed physical framework could also be applied to understand and simplify transistor hybrid integration.

Applications in Fast Computing of Complex Transistors

The above theory provides opportunities for fast computing or design aid of complex transistors. As a demonstration, a compiled HTML file is provided to calculate drain‐offset transistors, mid‐gate transistors, solid‐state vacuum triodes, split‐gate transistors, and transistor hybrid integration according to the input parameters (see Figures S4 and S5, Supporting Information). The calculated results presented in this manuscript could be obtained by using this file. As an example, split‐gate transistors have been made (e.g., with MoS2 or WSe2)[ , ] for fast sensing and computing applications and could be regarded as the gated/nongated/gated structure. A typical device structure is illustrated in Figure  . Denote the gate voltages as V G1 (near the source) and V G2 (near the drain) and the current is: here, V 1 and V 2 are the potential at the end and beginning of the two gated channels. Calculation methods are given in Note S6 (Supporting Information). Exemplary results of calculated transfer characteristics with the same set of parameters are presented by plotting the contours of I D and the voltage drop across the non‐gated channel V 2 ‐ V 1 in Figure 7d,e, which agree well with the 2D‐TCAD simulation shown in Figure 7b,c but consume about 1000 times less time. In particular, the asymmetric impacts of V G1 and V G2 on I and V 2–V 1 are clearly observed with details in Figure 7d,e, dashed ovals. Output characteristics are shown in Figure 7e–h. The results demonstrate that the simplified physical picture may provide a physical‐meaningful platform for few‐shot learning to train parameters and to model and predict the performance of complex transistors.

Figure 7

Exemplary results of fast computing split‐gate transistors. a) A schematic representation of the transistor structure. For transfer characteristics, b,d) the current I D and c,e) the potential drop V 2–V 1 at varied V G1 and V G2 with fixed V D = 6 V, where (b, c) is obtained from the TCAD simulation (0.5 V step) and (d, e) are from calculations by Equation (11) (0.05 V step). The computing time on the same computer is about 50 min and 2 s, respectively. For output scanning, the data for varied V D and V G2 with fixed V G1 = 6 V are shown in (f–i) in the same order.

For computing other transistors or transistor integration in Figure 1a, similar approaches could be applied by modifying Equation (5). For example, mid‐gate transistors and solid‐state vacuum triodes (or so‐called “static induction transistors”)[ , ] (Figure 1a) could be treated by rewriting Equation (5) corresponding to the nongated/gated/nongated structure (Note S7, Supporting Information). In general, mid‐gate transistors usually have Ohmic conduction in the non‐gated channels to allow Ohmic injection (e.g., Ga2O3 transistors[ ]), while static induction transistors usually have SCLC in the non‐gated channels to keep the low off‐current.

Conclusion

The charge transport of semiconductors in transistors with nontrivial gates or hybrid integration could be simplified and understood in the same physical picture of “charge carriers from gated into nongated semiconductors.” The conduction in the nongated semiconductors is a synergetic result of charge transport in the gated semiconductors and carrier relaxation, transit, and transport in the non‐gated semiconductors. A general theoretical framework is derived to describe I–V relation, current saturation, evolution of potential and drift field for various transistors with nontrivial gates or transistor–diode integration. Within the framework, how materials and device factors determine the performance could be briefly understood by: a) the space‐charge‐to‐free‐carrier ratio η as an indicator that characterizes how severely the charges injected from the gated semiconductor are limited by the transport in the nongated semiconductor; b) the charge transport factor α and charge density factor Q 0 that characterize the conduction mechanisms from Ohmic to SCLC and then to trap‐limited SCLC; c) the partial voltage coefficient γ that characterizes the voltage distribution between the coupled channels (an increased γ leads to an increased V 1 across the gated channel). The understanding has been verified by numerical simulations and agrees well with device experiments and a device calculator is demonstrated. Having general applicability, the approach may be combined with specific properties of semiconductors and devices and provides a straightforward way to quickly understand, model, design, and analyze complex transistors or hybrid integrations and the semiconductors in them.

Experimental Section

Device Simulation

The 2D‐TCAD simulations were performed by solving Poisson equations and continuity formula in fine grids. The device parameters are W = 1000 µm, L = 8 µm, d = 2 µm, t sc = 20 nm, µ 1 = µ 2 = 1 cm2 V‐1 s‐1, and C i = 11 nF cm–2. More details of simulation and fitting parameters are given in Tables S1–S3 and Notes S5and S6 in Supporting Information.

Device Fabrication

Drain‐offset transistors were fabricated based on amorphous N2‐doped InGaZnO4 semiconductor (t sc = 60 nm). The methods of fabrications and measurements are similar with our previous studies.[ ] Bottom‐gate, inverted staggered TFTs with an offset‐gate were fabricated on glass substrates. The electrodes are Mo (L = 200 µm, d = 100 µm, and W = 40 µm) and the dielectric layer is SiO2 (t ox = 300 nm). Gate electrodes were formed by the deposition of a 200 nm thick Mo layer that was subsequently patterned by wet etching. The gate insulator was then deposited by plasma‐enhanced chemical vapor deposition (PECVD). A 60 nm thick InGaZnO4 film was sputtered on the gate insulator and etched to form an active layer. The InGaZnO4 deposition was conducted under nitrogen gas to introduce nitrogen doping, which helped to improve the stability of InGaZnO4. In sputtering, the gas flow was Ar/O2/N2 = 30:0.5:1 in the unit of sccm with the power of 900 W. The source and drain electrodes were formed by sputtering and lift‐off processes. A passivation layer was deposited by PECVD and electrode holes were etched by reactive ion etching. Finally, the devices were annealed at 350 °C for 1 h in nitrogen atmosphere.

Transistor–photodiode integration was fabricated by integrating a vacuum‐deposited InGaZnO4 TFT and solution‐processed a vertical photodiode based on perovskite‐organics [ITO‐SnO2‐(FASnI3)0.6(MAPbI3)0.4‐poly(3‐hexylthiophene)‐Au]. The methods of synthesis of (FASnI3)0.6(MAPbI3)0.4, fabrication of photodiodes, and integration of photodiodes with TFTs are the same as described elsewhere.[ ] The parameters for experimental devices are: W = 1600 µm, L = 40 µm, d = 0.5 µm, t sc = 60 nm, t ox = 300 nm (SiO2), and V d = 0.1 V. The area S for a pixel of photodetector is 1925 µm × 1925 µm.

Si‐FET/ZnO–nanowire–emitter integration was fabricated by growing ZnO nanowires on the drain electrode of a MOSFET, as described elsewhere.[ ] N‐channel enhancement MOSFET (Infineon: BSP 324) was used for the high maximum‐rating drain–source voltage (400 V). The layers of Cr (200 nm) and Zn seed material (100 nm) were selectively deposited on the drain electrode of the MOSFET by sputtering. A solution was prepared by mixing zinc nitrate hexahydrate and hexamethylenetetramine (1:1) with the concentration of Zn2+ of 2 µmol L‐1. Then the substrates were suspended with top‐side down in the solution at 80 °C for 18 h for growing ZnO nanowires.

Device Characterization and Analysis

Drain‐offset transistors were measured for high‐voltage test by using a high‐voltage semiconductor test system (Keithley 2657A and Keithley 2450). In the drain‐offset InGaZnO4 transistors (Figure 6), the common parameters for fitting are: µ 1 = 10 cm2 V‐1 s‐1, µ 2 = 1 cm2 V‐1 s‐1, V th = 0.75 V, and the charge transport factor α = 2.34. The charge density factor Q 0 depending on V G are Q 0 = 1.3  ×  10–11, 1.1  ×  10–11, 9.9 ×  10–12, 8.2  ×  10–12, or 6.9  ×  10–12 C cm3, for V G = 30, 26, 22, 18, or 14 V.

For transistor–photodiode integration with a InGaZnO4‐TFT and a PSK‐photodiode, the electrical characteristics were characterized in air by a semiconductor parameter analyzer (Agilent, B1500A) in the dark or under illumination with a LED (wavelength 850 nm). The common parameters for fitting are: µ 1 = 8[1 − exp ( − (V Gt/17)2)] cm2 V‐1 s‐1 , µ 2 = 0.1 cm2 V‐1 s‐1, α = 1. The charge density factor Q 0 and threshold voltage V th depending on illumination power are Q 0 = 11.1 ×  10–7, 2.4 ×  10–7, 5.7  ×  10–8, 3.6  ×  10–8, and 2.9 ×  10–8 C cm‐3 and V th = ‐8.5, ‐7.8, ‐7.0, ‐6.8, or ‐6.5 V for P = 1374, 128.3, 3.02, 0.276, or 0 W.

For MoS2‐TFT and OLED integration, the parameters for calculating the transistor‐OLED integration are defined according to the reference:[ ] W = 300 µm, L = 4 µm, d = 0.1 µm, S = 0.09 × 0.09 = 0.0081 cm2, C i = 1.6  ×  10–7 F cm‐2 (50 nm Al2O3 with ε ox = 9ε 0), µ 1 = 18 cm2 V‐1 s‐1 (MoS2), V th = 4 V, µ 2 = 0.0005 cm2 V‐1 s‐1 (OLED), and V 0 = 3 V. Then, the I–V characteristics are calculated by Equations (5 and 7) with the factors as α = 2 and Q 0= 3  ×  10–13 C cm‐3 (ideal SCLC and ε SC = 3ε 0 for organic semiconductors).

For Si‐MOSFET and ZnO‐emitter integration, the field emission current of the ZnO nanowire in the integrated device was measured while they were being controlled by the Si‐MOSFET. The integrated device was placed in a high‐vacuum chamber (5 × 10−5 Pa). The anode current was probed by a monitored with a stainless‐steel probe (1 mm diameter) and biased by a power supply picoammeter (Keithley 6487).

Device Calculation

A calculator for different devices is compiled in an open‐source, HTML file with a user interface for demonstration and testing in the Supporting Information. Readers may open the “index” file to use it and read the “Manual” file for assistance. The calculator was tested by comparing some results with those obtained from TCAD simulations with varied device or material parameters. The calculations and fittings in this manuscript could be obtained by setting the corresponding parameters in this calculator. The calculator could be used to fit the experimental data or predict performance of some transistors. When calculating the split‐gate transistors, the device has the dimension of L 1 = 8 µm, d = 2 µm, and L 2 = 8 µm, with other parameters as the same as those in the drain‐offset transistors.

Conflict of Interest

The authors declare no conflict of interest.

Supporting Information2

Click here for additional data file.

Supporting Information2

Click here for additional data file.