| Literature DB >> 30143693 |
Nihar R Pradhan1,2, Carlos Garcia3,4, Bridget Isenberg3,5, Daniel Rhodes3,4, Simin Feng6, Shahriar Memaran3,4, Yan Xin3, Amber McCreary7, Angela R Hight Walker7, Aldo Raeliarijaona8, Humberto Terrones8, Mauricio Terrones6,9,10,11, Stephen McGill3, Luis Balicas12,13.
Abstract
We fabricated ambipolar field-effect transistors (FETs) from multi-layered triclinic ReSe2, mechanically exfoliated onto a SiO2 layer grown on p-doped Si. In contrast to previous reports on thin layers (~2 to 3 layers), we extract field-effect carrier mobilities in excess of 102 cm2/Vs at room temperature in crystals with nearly ~10 atomic layers. These thicker FETs also show nearly zero threshold gate voltage for conduction and high ON to OFF current ratios when compared to the FETs built from thinner layers. We also demonstrate that it is possible to utilize this ambipolarity to fabricate logical elements or digital synthesizers. For instance, we demonstrate that one can produce simple, gate-voltage tunable phase modulators with the ability to shift the phase of the input signal by either 90° or nearly 180°. Given that it is possible to engineer these same elements with improved architectures, for example on h-BN in order to decrease the threshold gate voltage and increase the carrier mobilities, it is possible to improve their characteristics in order to engineer ultra-thin layered logic elements based on ReSe2.Entities:
Year: 2018 PMID: 30143693 PMCID: PMC6109127 DOI: 10.1038/s41598-018-30969-7
Source DB: PubMed Journal: Sci Rep ISSN: 2045-2322 Impact factor: 4.379
Figure 1(a) Scanning transmission electron microscopy (STEM) image of an exfoliated ReSe2 single-crystal displaying a chain-like atomic arrangement. (b) Electron diffraction pattern for a ReSe2 single-crystal when the incident electron-beam is perpendicular to the planar atomic arrangement showing a rectangular planar Brillouin zone. (c) Micrograph of a typical few layered ReSe2 single-crystal exfoliated onto SiO2 which from AFM (inset) had a step height of 2.7 nm, or was four layers thick (for an inter-planar lattice separation c = 0.6702 nm[5]). (d) Micrograph of the same crystal after deposition of the electrical contacts which consisted of 50 nm of Au on a 5 nm layer of Cr. The larger electrical contacts were used to source (S) and drain (D) the current Ids when performing two-terminal measurements. The smaller contacts V1 and V2 were used for voltage sensing in four-terminal measurements. For this sample, the separation between the current leads was L 10.5 μm, the width of the channel was w 3.6 μm and the separation between voltage leads was l 4.5 μm. (e) Raman spectra of a ReSe2 monolayer. Given that inversion symmetry was the only symmetry operation present in the monolayer, in few-layers and in the bulk, there was just one Raman active irreducible representation, i.e. Ag. Therefore, all peaks were associated with Raman Ag modes. (f) Raman spectra for a crystal composed of five atomic layers. (g) Theoretical Raman spectra for monolayer (red) and bulk (blue) ReSe2.
Figure 2(a) Drain to source current Ids as a function of the gate-voltage Vbg for a ten layer thick ReSe2 crystal. Blue (magenta) markers depict decreasing (increasing) gate-voltage sweeps. Notice the near absence of hysteresis. Both traces were acquired at room temperature under a bias voltage of Vds = 50 mV. Inset: picture of the FET indicating the configuration of contacts. Source (S) and drain (D) contacts were used for two terminal measurements. The channel length and width of the device was 11.6 μm and 10.9 μm respectively. (b) Ids as a function of Vbg for the same sample and for several temperatures ranging from T = 300 K to 2 K. Notice the progressive emergence of a threshold gate-voltage which increases upon decreasing T. (c) Drain to source current Ids for a n = 4 sample as a function of the back-gate voltage Vbg in a semi-logarithmic scale for several values of the bias voltage Vds, measured at T = 275 K through a two-terminal configuration. (d) Same as in (c) but measured via a four-terminal configuration. (e) Ids as a function of Vbg for several temperatures measured via a two-terminal configuration in a linear scale. (f) Same as in (e) but in a logarithmic scale and measured through a four-terminal configuration. For both panels (e) and (f) a bias voltage Vds = 0.3 V was used.
Figure 3Electron- and hole- mobilities as a function of the temperature as extracted from the MOSFET transconductance formula for a (a) n = 10 and a (b) 4-layers thick sample. In (a) magenta and blue markers depict electron- and hole-mobilities respectively, as extracted from a two-terminal configuration under Vds = 50 mV. In (b) dark cyan and brown markers depict hole- and electron mobilities, respectively. Solid and open circles indicate mobilities extracted from two- and four-terminal configurations, respectively. The drain to source voltage applied to the 4 layer sample was Vds = 0.3 V.
Figure 4(a) Drain to source current Ids normalized by a power of the temperature T as a function of the charge q = e for the n = 10 layers sample and for several positive values of the back gate voltage Vbg. (b) Same as in (a) but for negative values of Vbg. Both data sets in (a) and in (b) were measured under Vds = 50 mV. In both panels red lines are linear fits from which we extracted the gate voltage dependence of the Schottky barrier ϕSB (Vbg) between metallic contacts and the semiconducting channel. (c) ϕSB as a function of Vbg, showing that in the limit of high gate voltages (flat band condition), the extracted Shottky barriers ΦB were ~200 meV for holes and ~16 meV for electrons respectively. (d) Conductivity σ = Ids/Vds l/w, where l and w are length and width of the semiconducting channel respectively, as a function of 1/T1/3 and for several gate voltages. Dark red lines are linear fits indicating that at lower temperatures the conductivity as a function of T can be described by the two-dimensional variable range hopping expression.
Figure 5Phase-modulation based on a four-layer ambipolar ReSe2 FETs. (a) Ids as a function of Vbg for a few-layer ReSe2 field effect-transistor at T = 275 K. This trace was acquired under a drain supply voltage Vdd = 50 mV. Inset depicts the scheme of measurements where Rload is a load resistor and Vdd is the bias voltage. Vin-ac, which is a superposition of DC and AC (~1.5 V) biases, was applied to the back-gate while Vout corresponds to the read-out voltage. Magenta squares indicate the DC back-gate voltages chosen to superimpose an oscillatory AC signal to extract the relative phase-shift between Vin and Vout. (b) Relative phase shift as a function of Vbg. By increasing Vbg from negative values we tuned the phase-shift to 90° and then to ~180°. This is clearly illustrated by panels (c,d) and (e) which display Vin (black traces) and Vout (blue traces) as a function of time t for various gate voltages.