| Literature DB >> 29330736 |
Shengkai Wang1, Xianwen Sun2, Guanghui Li1, Caihong Jia1, Guoqiang Li1, Weifeng Zhang3.
Abstract
Pt/Nd:SrTiO3 (STO)/In devices were fabricated by depositing Schottky-contact Pt and Ohmic-contact In electrodes on a single crystal STO with Nd doping. The Pt/Nd:STO/In devices show multi-level resistance-switching (RS) memory and memory-state-dependent photovoltage (PV) effects, which can be controlled by the applied pulse width or magnitude. Both the RS and PV are related to the bias-induced modulation of the interface barrier, both in height and width, at the Pt/Nd:STO interface. The results establish a strong connection between the RS/PV effects and the modulation of the Nd:STO interface triggered by applied electric field and provide a new route by using an open-circuit voltage for non-destructively sensing multiple non-volatile memory states.Entities:
Keywords: Interface state; Multi-level memory; Photovoltage; Resistive switching
Year: 2018 PMID: 29330736 PMCID: PMC5766446 DOI: 10.1186/s11671-018-2433-5
Source DB: PubMed Journal: Nanoscale Res Lett ISSN: 1556-276X Impact factor: 4.703
Fig. 2The I–V characteristics of a the In/Nd:STO/In and b Pt/Nd:STO/In devices in the voltage range from 0 V → 5 V → 0 V → − 5 V → 0 V with 50-mA compliance current. The inset shows the device schematic illustration
Fig. 1a The XRD patterns and b Raman spectra of undoped STO and Nd-doped STO single crystal
Fig. 3Consecutive RS cycles a from LRS to HRS and b from HRS to LRS. The device was firstly set to LRS (HRS) by a − 5 V (+ 5 V) pulse with 100 ms width and then applied by a + 5 V (− 5 V) pulse with varied pulse widths of 100 ns, 10 μs, and 10 ms, respectively. The corresponding resistance transition from LRS (HRS) to intermediate resistance states or HRS (LRS). c R–V hysteresis loops controlled by pulse voltage. The Pt/Nd:STO/In device was firstly set to LRS by a pulse of − 3 V, followed by sweeping the pulse to + 2 V (or + 3, + 4, and + 5 V) and back to − 3 V with 100-ms pulse width. All the resistance was read at 0.1 V
Fig. 4The I–V curves in the low-bias regime (− 0.6 to + 0.6 V) after switching with a series of voltage pulses from + 1 to + 5 V with 100 ms (switching from LRS to intermediate resistance states and to HRS) under a the light illumination and b dark, respectively
Fig. 5Schematic diagram of energy band structure and interface state Pt/NSTO/In system at HRS and LRS. The red hollow and solid spheres at interface represent the unoccupied and occupied interface state, respectively