Boosting Hole Mobility in Coherently Strained [110]-Oriented Ge-Si Core-Shell Nanowires.

The ability of core-shell nanowires to overcome existing limitations of heterostructures is one of the key ingredients for the design of next generation devices. This requires a detailed understanding of the mechanism for strain relaxation in these systems in order to eliminate strain-induced defect formation and thus to boost important electronic properties such as carrier mobility. Here we demonstrate how the hole mobility of [110]-oriented Ge-Si core-shell nanowires can be substantially enhanced thanks to the realization of large band offset and coherent strain in the system, reaching values as high as 4200 cm2/(Vs) at 4 K and 1600 cm2/(Vs) at room temperature for high hole densities of 1019 cm-3. We present a direct correlation of (i) mobility, (ii) crystal direction, (iii) diameter, and (iv) coherent strain, all of which are extracted in our work for individual nanowires. Our results imply [110]-oriented Ge-Si core-shell nanowires as a promising candidate for future electronic and quantum transport devices.

The epitaxial growth of high-quality Ge–Si core–shell nanowires (NWs) provides a unique opportunity for improving control over charge transport in nanostructures.[1−4] In addition, the strain induced by the lattice mismatch between Ge and Si (around 4%) modifies the band alignment,[5,6] paving the way to technological applications based on band gap engineering.[7−10] However, the lattice mismatch between Ge and Si results in strain-induced misfit dislocations,[11] severely affecting the carrier mobility. Therefore, it is crucial to minimize defect formation in order to profit from the enhanced mobility of hole carriers from the enhanced confinement in the system.

An important factor that determines both the morphology and the electrical properties of Ge–Si core–shell NWs is the growth orientation. So far, most studies have focused on [111]-oriented nanowires, because this is the preferred nanowire growth direction.[12] However, mechanical calculations of the critical shell geometry in the Ge–Si core–shell system predict that the largest range of defect-free shell thicknesses can be achieved with the [110] orientation.[13] In addition, [110]-oriented NWs have also been predicted to exhibit enhanced functionalities for electronic applications due to the spatial separation of carriers,[6] because the localization of the wave functions from the upper part of the valence band and the lower part of the conduction band can differ substantially depending on orientation.[14,15] Here we report how the hole mobility of coherently strained [110]-oriented Ge–Si NWs can be substantially higher than their [111] counterparts. We optimize the nanowire growth simultaneously with the understanding of their strain relaxation mechanism. The direct correlation between structural and mobility measurements unambiguously reveals the high quality of [110]-oriented Ge–Si NWs.

The growth procedure is divided into three main steps (Figure a). The first step is the vapor liquid solid (VLS) growth of Ge NWs on a (111) Ge substrate from Au colloids to act as core for the subsequent Si shell growth. To eliminate amorphous sidewall deposition and to achieve high quality NW growth with low density of defects (lower than 0.08 μm–1), we adopt an in situ HCl etching scheme combined with a reported multiple-temperature procedure.[16,17] Further information can be found in the Supporting Information Section I. Under these conditions, three different growth orientations are obtained: [111], [110], and [112] (see Supporting Information Section III). Moreover, the nanowire orientation is strongly correlated with the Ge core radius r:[18,19] for r > 10 nm, most NWs grow along the [111] direction, while for values of r < 10 nm, the [110] and [112] directions are preferred. The second step is the growth of a Si axial separation segment.[20] The final step is the growth of the Si shell around the Ge core at a temperature of 690 °C assisted by HCl. During this process, the Au atoms end up trapped in the Si separation segment, avoiding diffusion into the Ge–Si system. We note that the combination of the separation segment and HCl is essential to avoid impurity atoms incorporation into the Ge–Si system.[18,21] This is especially important for [110]-oriented NWs, which exhibit preferential catalyst incorporation as compared with [111]-oriented NWs.[22]

Figure 1

Growth strategy and composition. (a) Schematic illustration of the growth procedure adopted for the Ge–Si core–shell growth. (b) High-angle annular dark-field image of a representative Ge–Si core–shell NW. (c,d) Atom probe tomography maps along the axial and the radial (cross-section) directions, respectively.

Figure b shows a high-angle annular dark-field (HAADF) image of a representative [110]-oriented Ge–Si core–shell NW, where we can observe the highly uniform Si shell around the Ge core. During VLS growth, the incorporation of Au into the NW can take place and for this reason we have checked the Ge NWs with atom probe tomography (APT). Figure c,d displays APT maps along the axial and the radial (cross-section) directions, respectively. The Ge–Si core–shell compositional information is also shown for a specific location along the nanowire axis (Figure c (dashed line)). APT results indicate that Au diffusion during the Si shell growth has been extremely reduced (more than 4 orders of magnitude) by this approach with respect to standard Ge–Si core/shell NWs (see Supporting Information Table 1).

The best crystalline quality is observed for the thinnest nanowires with a Ge core radius of around 5 nm and Si shell of 2 nm. Figure a displays a high-resolution transmission electron microscopy (HRTEM) image of one representative thin nanowire. The calculated fast Fourier transform reveals that the nanowire grows along the [110]-direction (Figure b). Theoretical calculations[23] indicate that [110]-oriented NWs for this specific thin morphology should belong to the coherent regime. On the other hand, [111]-oriented NWs with the Ge core radius being larger than 10 nm and with a Si shell ranging between 5 and 6 nm are predicted by the same calculations to lie in the incoherent region and thus should exhibit misfit dislocations.

Figure 2

Strain characterization. (a,b) HR-TEM image of a [110]-oriented Ge–Si core–shell NW in [11̅0] projection and the corresponding fast Fourier transform, respectively. (c,d) the ε and ε strain field maps, respectively. Si shell has been chosen as a reference. The x-axis is taken parallel to [002̅] and the z-axis parallel to [110]. (e,f) Line profiles (marked by an arrow) and averaged in the dashed black rectangle, respectively.

This effect has been verified with a dedicated series of growths. We plot the density of misfit dislocations as a function of the Ge core radius (see Supporting Information Figure 2a). We have kept the shell thickness constant at 2 nm and focused on the effect of varying the Ge core radius. The main motivation for this choice is that the value of the Ge core radius, besides strain, also affects the growth direction and with that the elastic properties of the core–shell system. The results indicate that NWs with r < 10 nm mostly grow along the [110] directions, accommodating strain without nucleating defects as opposed to the other orientations.

To understand how strain affects in [110]-oriented NWs, we apply the geometrical phase analysis (GPA) technique.[24] Our measurements indicate that the Ge core is under a tensile strain along the radial direction, whose magnitude is ε ∼ 3.5% (Figure d), while along the growth direction, the Ge core exhibits a compressive strain by an amount of ε ∼ −1.5% (Figure f). No misfit dislocations are visible at the interface between Ge and Si, unravelling the coherent strain relaxation mechanism.

The next step comprises the crystalline quality assessment by combining electrical transport (Supporting Information Section V) and transmission electron microscopy measurements. The hole mobility μ is extracted from a series of current–voltage measurements (I–VG) at a fixed source-drain bias VSD in the linear regime of operation of the device. Figure a (Figure b) shows multiple I–VG measurements for Device #9 (Device #1) at 4 K. The current I at VG = 0 V for Device #9 with a [110] crystal orientation is at least a factor of 3 higher than for Device #1 with a [111] crystal orientation. The average transconductance Gt(VSD) is calculated by performing a least-squares linear fit on the data, see Figure a,b. Because μ ∝ Gt(VSD)/VSD, this allows us to determine μ for many VSD that are then averaged to obtain the μ values in Figure c,d. For more information on the method used to determine μ, refer to the Supporting Information Section V. The mobilities in Figure c are measured at 4 K and vary from typically 200–800 cm2/(V s) for nanowires with diameters d > 25 nm and from 1500 to 4200 cm2/(V s) for nanowires with diameters d < 25 nm. For the mobilities measured at room temperature, the ranges are 200–400 and 800–1600 cm2/(V s), respectively (Figure d). While the measured hole mobilities remain slightly lower in these Ge–Si core–shell NWs compared to ultrapure bulk Ge (1900 cm2/(V s) at RT),[25] our mobility values are extremely high taking the carrier concentration (1019 cm–3) into account (see Supporting Information Section V for more details concerning the estimation of the hole density). In addition, the mobilities of our NWs exceed previously reported maximum values, 730,[26] 600,[27] and 500 cm2/(V s) for room temperatures and 1800 cm2/(V s) at 77K[7,8]

Figure 3

Direct correlation between crystal direction and mobility. (a) I versus VG at 4K for Device #9 with a [110] crystal orientation and (b) for Device #1 with a [111] crystal orientation. VSD is varied from 1 to 10 mV in steps of 1 mV. For each curve, a least-squares linear fit (dotted lines) is performed between the fitting limits denoted by the vertical lines and arrows. Only the blue curves and the corresponding fits are used in the final calculation of μ, see Supporting Information for details. (c,d) Hole mobility μh versus wire diameter for 33 different nanowires from the same growth batch. The outer diameter has been measured with atomic force microscopy. The red open diamonds and the green open circles correspond to those specific devices that have been analyzed by HRTEM. (e,f) HRTEM (left panels) and HR-STEM (HAADF) (right panels) images for the cross-section of two representative NWs with small and large Ge core radius, respectively. The atomic arrangement further confirms their growth direction as [110] and [111] in Figure e,f, respectively.

To unambiguously identify the growth orientation of the specific NWs used in the transconductance measurement, a total of nine devices were sliced open using focused ion beam and then analyzed in TEM (see Supporting Information Section IV). Figure c,e shows HRTEM images of two selected sliced devices, exhibiting high and low mobilities (Figures a,b), respectively. The determination of distances and angles between the Bragg reflections measured through the corresponding FFT, allows identification of the growth direction. A key feature is that nanowires exhibiting high mobilities all grow along the [110] direction, while [111] is adopted for the low mobility NWs. The atomic arrangement obtained from high-resolution scanning TEM-HAADF (Figure d,f) further confirms their growth direction.

To further assess the correlation between crystalline quality and electronic transport measurements we controllably define quantum dots inside a nanowire device (Figure a). The nanowire has a diameter of 20 nm (see Supporting Information Section V). The voltages on the outer two bottom gates 1 and 6 are set at Vg1 = 2.65 V and Vg6 = 3.25 V to create local tunnel barriers defining an island in the nanowire, while nanowire segments above gates 2, 4, and 5 are kept highly conductive by setting the corresponding gate voltages at −1 V. Figure b displays the numerical differential conductance dI/dVSD versus the voltage on gate 3 Vg3 and source drain voltage VSD measured at 10 mK.

Figure 4

One hundred and fifty charge transitions in a highly stable quantum dot. (a) Scanning electron microscopy image in false color of a nanowire with two Ti/Pd ohmic contacts (S,D) and 6 bottom gates g1–g6, which are covered with 10 nm Al2O3. (b) Numerical differential conductance dI/dVSD versus VSD and Vg3, displaying 150 very well-defined, closing Coulomb diamonds. (c) Coulomb peak spacing ΔVg3 extracted from (b) versus the number of depleted holes N. (d) Numerical differential conductance dI/dVSD versus VSD and Vg2 of a second device with diameter of 30–35 nm, displaying Coulomb diamonds with much more switching events than in (b).

The conductance plot contains a set of 150 diamond-shaped regions in which the current is blocked due to Coulomb blockade and the number of holes N on the island is fixed. The finite conductance outside the diamonds corresponds to sequential single-hole tunnelling through this 500 nm long quantum dot.[28] By sweeping Vg3 from −2 to +2 V, we push a total of 150 holes off the island. Only three charge switches appear in this 30 h measurement (at −0.2, +0.7, +1.1 V) and the conductance as well as the diamonds’ shapes and sizes show very little variation over the entire voltage range. To quantitatively confirm this robustness, Figure c depicts the spacing ΔVg3 between two adjacent Coulomb peaks versus the number of depleted holes, starting at Vg3 = −2 V. The first 120 values of ΔVg3 nearly all fall between 23 and 28 mV, neatly following the constant-interaction model. After the depletion of 120 holes, the peak spacing varies more, which can be explained by shell filling.[29] This very stable behavior could also be reproduced in a second nanowire of the same diameter. To elucidate the importance of the 3–4 times higher mobility of the small [110] nanowires, Figure d shows a bias spectroscopy at 4 K of a nanowire with a diameter of 30–35 nm fabricated in the same way as the device in Figure a. While the Coulomb diamonds indicate the formation of a gate-defined quantum dot between gates g1 and g3, approximately 10–20 switching events are visible over this 1.4 h measurement, corresponding to about one switching event every 5 min. This strongly increased switching frequency can be explained by the finite defect density in the thicker [111] nanowires, where the defects can act as charge traps that randomly change the electrostatic environment of the dot. This behavior is representative for our measurements on several devices made from nanowires with diameters of 30–40 nm. The significant increase in the measurement stability suggests that the 3- to 4-fold mobility increase in the thinner nanowires makes a vital difference for the usability of these nanowires in quantum transport experiments and future spintronic applications. All together (Figure ) indicates a very robust behavior to the low defect density in the nanowire.

In summary, we have demonstrated how coherently strained [110]-oriented Ge–Si NWs exhibit substantially enhanced hole mobility, exceeding previously reported values. We believe that our results offer crucial advantages as buildings blocks in electronic nanodevices compared to existing core–shell systems, that is, spin–orbit energy is expected to be dramatically enhanced in this system when the strain is conserved in the Ge core.[30]