| Literature DB >> 23857266 |
Bashar Yafouz1, Nahrizul Adib Kadri, Fatimah Ibrahim.
Abstract
During the last three decades; dielectrophoresis (DEP) has become a vital tool for cell manipulation and characterization due to its non-invasiveness. It is very useful in the trend towards point-of-care systems. Currently, most efforts are focused on using DEP in biomedical applications, such as the spatial manipulation of cells, the selective separation or enrichment of target cells, high-throughput molecular screening, biosensors and immunoassays. A significant amount of research on DEP has produced a wide range of microelectrode configurations. In this paper; we describe the microarray dot electrode, a promising electrode geometry to characterize and manipulate cells via DEP. The advantages offered by this type of microelectrode are also reviewed. The protocol for fabricating planar microelectrodes using photolithography is documented to demonstrate the fast and cost-effective fabrication process. Additionally; different state-of-the-art Lab-on-a-Chip (LOC) devices that have been proposed for DEP applications in the literature are reviewed. We also present our recently designed LOC device, which uses an improved microarray dot electrode configuration to address the challenges facing other devices. This type of LOC system has the capability to boost the implementation of DEP technology in practical settings such as clinical cell sorting, infection diagnosis, and enrichment of particle populations for drug development.Entities:
Mesh:
Year: 2013 PMID: 23857266 PMCID: PMC3758635 DOI: 10.3390/s130709029
Source DB: PubMed Journal: Sensors (Basel) ISSN: 1424-8220 Impact factor: 3.576
Figure 1.A schematic illustration of the responses of polarizable particles to a non-uniform electric field, provided that εp1 > εm > εp2; εm, εp1 and εp2 are the permittivities of the medium, particle 1 and particle 2, respectively.
Figure 2.A schematic diagram of the movement of particles within the dot microelectrode device when experiencing (A) negative DEP, (B) positive DEP. Reproduced with permission from [75].
The procedure for fabricating a gold microelectrode using a positive photoresist with the photolithography process.
| Step 1: | Soak the gold-coated glass slides first in acetone, then in methanol and then in DI H2O with 5 minutes of ultrasonic agitation at each step. Then, dry the slides on a hotplate at 120 °C for 10 minutes. |
|
| |
| Step 2: | Coat the slides with a positive photoresist using a vacuum spin coater. Set the spin coater parameters to 3,000 rpm and 30 seconds. |
|
| |
| Step 3: | Lay the slides on a hotplate for 60 seconds at 100 °C. |
|
| |
| Step 4: | Expose the slides to UV light through the photomask for 40 seconds. |
|
| |
| Step 5: | Immerse the exposed slides into the developer solution for a few seconds only, and then rinse the slides with DI H2O to avoid an overreaction. A longer developing time has an adverse effect on the unexposed gold layer. |
|
| |
| Step 6: | Place the slides in a convection oven for 45 minutes at 90 °C. |
|
| |
| Step 7: | Dip the slides into gold etchant, removing them once the exposed gold has been washed away. Rinse the slides with DI H2O. |
|
| |
| Step 8: | Place the etched slides in boiled 18% HCl until the seed layer has bubbled away. Rinse the slides with DI H2O. |
|
| |
| Step 9: | Remove any leftover photoresist using a positive photoresist stripper solution for 5–10 seconds. Rinse the slides with DI H2O and dry them. |
|
| |
| Step 10: | Dispose of all solutions safely. |
Figure 3.Images of the key steps in the fabrication of planar electrodes by photolithography, including (A) photoresist coating, (B) UV exposure, (C) developing, (D) etching, and (E) stripping.
Figure 4.A schematic illustration of the proposed 4×4 microarray dot electrode geometry used in our LOC device.
Figure 5.Simulation of electric field distribution over the dot electrode: (A) without ground plane between dot apertures; (B) with ground plane between dot apertures. Reproduced with permission from [74].
Figure 6.A schematic diagram of the proposed LOC device.
Design specifications of the different layers of the proposed LOC device.
|
| ||||
|---|---|---|---|---|
| Top Layer | PMMA | 60 | 40 | 4 |
| ITO Layer | ITO | 45 | 15 | 1 |
| Spacer | Polyresin | 38 | 15 | 0.1 |
| Electrode | Gold | 38 | 26 | 1 |
| Bottom Layer | PMMA | 60 | 40 | 4 |