Sensitivity of Inner Spacer Thickness Variations for Sub-3-nm Node Silicon Nanosheet Field-Effect Transistors.

The inner spacer thickness (TIS) variations in sub-3-nm, node 3-stacked, nanosheet field-effect transistors (NSFETs) were investigated using computer-aided design simulation technology. Inner spacer formation requires a high selectivity of SiGe to Si, which causes inevitable TIS variation (ΔTIS). The gate length (LG) depends on the TIS. Thus, the DC/AC performance is significantly affected by ΔTIS. Because the effects of ΔTIS on the performance depend on which inner spacer is varied, the sensitivities of the performance to the top, middle, and bottom (T, M, and B, respectively) ΔTIS should be studied separately. In addition, the source/drain (S/D) recess process variation that forms the parasitic bottom transistor (trpbt) should be considered with ΔTIS because the gate controllability over trpbt is significantly dependent on ΔTIS,B. If the S/D recess depth (TSD) variation cannot be completely eliminated, reducing ΔTIS,B is crucial for suppressing the effects of trpbt. It is noteworthy that reducing ΔTIS,B is the most important factor when the TSD variation occurs, whereas reducing ΔTIS,T and ΔTIS,M is crucial in the absence of TSD variation to minimize the DC performance variation. As the TIS increases, the gate capacitance (Cgg) decreases owing to the reduction in both parasitic and intrinsic capacitance, but the sensitivity of Cgg to each ΔTIS is almost the same. Therefore, the difference in performance sensitivity related to AC response is also strongly affected by the DC characteristics. In particular, since TSD of 5 nm increases the off-state current (Ioff) sensitivity to ΔTIS,B by a factor of 22.5 in NFETs, the ΔTIS,B below 1 nm is essential for further scaling and yield enhancement.

1. Introduction

Silicon fin-shaped field-effect transistors (FinFETs) have been continuously scaled down from 22-nm to 5-nm nodes using fins with high aspect ratios and design technology co-optimization [1,2,3,4,5,6]. However, increasing the fin aspect ratio is challenging owing to the process complexity, and FinFETs with narrow fins exhibit threshold-voltage variations and performance degradation induced by the quantum confinement effect [7,8,9,10]. By contrast, Silicon gate-all-around nanosheet field-effect transistors (NSFETs) have received considerable attention as promising devices that can replace FinFETs in sub-3-nm nodes, as they can overcome these limitations through stacked nanosheet (NS) channels [11]. Furthermore, NSFETs provide excellent electrostatics because the gate surrounds the NS channels and drives a larger current within the same footprint with a wider effective channel width than FinFETs [11,12].

The inner spacer is a distinctive structural feature of NSFETs that has not been employed in previous devices. Typically, selective etching of the SiGe sacrificial layers is performed to form the inner spacer. However, selective etching requires a high selectivity of SiGe to Si and lateral etching. Therefore, it can be vulnerable to process variations [13,14]. Furthermore, because the inner spacer determines the gate length (LG), these variations result in NSFETs with unintended LG changes and cause unoptimized leakage and DC/AC performance [11,15]. Therefore, precise control of the inner spacer thickness (TIS) is crucial for performance optimization.

Previous studies related to the inner spacer have focused on the electrical properties of NSFETs, assuming the same shape and thickness from the top inner spacer to the bottom inner spacer [11,15]. However, in the actual process, the TIS variation (ΔTIS) may not occur uniformly [11,16]. In addition, for three-stacked NSFETs, the top and middle inner spacers adjoin two adjacent NS channels, while the bottom inner spacer adjoins only one NS channel and a punch-through stopper (PTS) region. Thus, the thickness variations of the top/middle/bottom (T/M/B) inner spacers have different effects on the device behavior; i.e., the T/M/B ΔTIS (ΔTIS,T/ΔTIS,M/ΔTIS,B) have different effects on the performance. Therefore, the performance sensitivities must be studied separately. Additionally, the over-etched S/D recess is a crucial factor determining the effects of the parasitic bottom transistor (trpbt) on the DC performance [17]. The effects of trpbt on performance become more pronounced as LG decreases, which is a potential threat for further scaling [17,18]. However, there have been no studies on the effects of the S/D recess depth (TSD) along with T/M/B ΔTIS on the device behavior. In this study, for the first time, we comprehensively analyzed the sensitivity of the DC/AC characteristics to each ΔTIS considering the TSD, and the off-state characteristics were analyzed in detail using fully calibrated computer-aided design (TCAD) simulation technology [19].

2. Device Structure and Simulation Methodology

The sub-3-nm node NSFETs investigated in this study were simulated using Sentaurus TCAD tools. The following physical models were considered in the TCAD simulation:

The drift–diffusion model was considered using Poisson’s equations and the continuity equations to determine the electrostatic potential and carrier transport.

The density gradient model was considered for the quantum confinement effect in the drift-diffusion model [20,21].

The Slotboom bandgap narrowing model was considered for doping-dependent bandgap narrowing in Si and SiGe [22,23].

A low-field ballistic mobility model was considered for quasi-ballistic transport [24].

Mobility degradation at the interfaces was considered for remote phonon scattering and remote Coulomb scattering [25].

The inversion and accumulation layer mobility models were considered for Coulomb impurity, phonon scattering, and surface roughness scattering [26].

A high-field saturation model was considered for carrier velocity saturation under a strong electric field [27].

The deformation potential model was considered for the strain-induced density of states, effective mass of carriers, and energy-band shift [28].

The Auger and Shockley–Read–Hall (SRH) recombination models were used.

Figure 1a shows schematics of the sub-3-nm node 3-stacked NSFETs. Among the T/M/B ΔTIS, we varied only one of the T/M/B TIS, with the others fixed at 5 nm, to investigate the effects of the T/M/B ΔTIS on the DC/AC characteristics separately. Here, the thicknesses of the T/M/B inner spacers were defined as TIS,T, TIS,M, and TIS,B, respectively. In addition, TSD of 0 and 5 nm were used to consider the effects of TSD on the performance along with those of ΔTIS [14]. Therefore, a comprehensive analysis of ΔTIS considering the TSD effect was performed.

Figure 1

(a) Structure of NSFETs with the TSD and cross-sectional views. (b) Schematics of ΔTIS and its definition.

The TIS without variation (TIS,ref) was set as 5 nm, and only one of the three TIS was varied from 3 to 7 nm (Figure 1b). In this study, ΔTIS was defined as TIS − TIS,ref, and the LG of each channel depended on ΔTIS (LG = 22 − 2 × (TIS,ref + ΔTIS)). Si0.98C0.02 (Si0.5Ge0.5) S/D doped with phosphorus (boron) at 4 × 1020 cm−3 was used for the NFETs (PFETs). The contact resistance of the S/D was set as 1 nΩ·cm2. The PTS layer was doped at 3 × 1018 cm−3, and the drain voltage (Vds) was fixed at |0.7| V. The geometric parameters are presented in Table 1. The NSFETs were calibrated to TSMC’s 5-nm node FinFETs [5], and the same physical parameters were used, as shown in our previous studies [29]. The drain current was fitted by adjusting the doping profile, ballistic coefficient, and saturation velocity. The doping profile was changed to fit the subthreshold swing and DIBL since the doping profile is deeply concerned with the device behaviors in the subthreshold region. The ballistic coefficient was tuned to fit the drain current in the linear region, and the saturation velocity was set to fit the drain current in the saturation region. We extracted the on-state current (Ion) and gate capacitance (Cgg) at |Vgs| = 0.7 V and |Vds| = 0.7 V. Moreover, the off-state current (Ioff) and parasitic capacitance (Cpara) were extracted at |Vgs| = 0 V and |Vds| = 0.7 V.

Table 1

Geometric parameters for sub-3-nm node NSFETs.

Fixed Parameters	Values
Contact poly pitch (CPP)	42 nm
Fin pitch (FP)	60 nm
Gate length (LG)	12 nm
Spacing thickness (TSP)	10 nm
NS thickness (TCH)	5 nm
NS width (WNS)	25 nm
Interfacial layer thickness (TIL)	0.6 nm
HfO2 thickness (THK)	1.1 nm
TIS without variation (TIS,ref)	5 nm
S/D doping concentration (NSD)	4 × 1020 cm−3
PTS doping concentration (NPTS)	3 × 1018 cm−3
Variable parameters	Values
Excess S/D recess depth (TSD)	0 or 5 nm
Inner spacer thickness (TIS)	3–7 nm

3. Results and Discussion

Figure 2 shows the transfer curves of NSFETs with different TIS,B for TSD = 0 and 5 nm. No significant dependence of the DC performance on ΔTIS,B was observed at TSD = 0 (Figure 2a). By contrast, at TSD = 5 nm, the Ioff increased significantly as TIS,B increased (Figure 2b). The TSD typically impacts the Ioff of trpbt [17], where TIS,B determines the LG of trpbt. Because the LG of trpbt affects the gate controllability over the PTS region, an increase in ΔTIS,B significantly degrades the DC performance. As an increase in TSD degrades the gate controllability of trpbt, TIS,B is a critical factor determining the parasitic punch-through current (Ipt) in the PTS region. Therefore, the subthreshold swing and DIBL are significantly degraded, as shown in the inset of Figure 2 and Table 2.

Figure 2

Transfer curves of the NSFETs having different TIS,B with (a) TSD = 0 nm and (b) TSD = 5 nm.

Table 2

DIBL of NSFETs according to the TIS,B and TSD.

Type	TIS,B [nm]	DIBL [mV/V]
		TSD = 0 nm	TSD = 5 nm
NFETs	3	60	67
	5	62	72
	7	67	81
PFETs	3	51	54
	5	53	57
	7	58	61

The Ioff sensitivities to the T/M/B ΔTIS (SIoff,T/SIoff,M/SIoff,B) are compared in Figure 3. We defined SIoff as the slope of Ioff−ΔTIS, which indicates how sensitively Ioff varies with respect to ΔTIS. For the NFETs with TSD = 0 nm, the SIoff,T (0.208) and SIoff,M (0.228) slightly exceeded the SIoff,B (0.104 nA/nm), and similar SIoff tendencies were observed for the PFETs. The TSD variation not only increased Ioff, but also significantly increased SIoff,B for both the NFETs and the PFETs. The SIoff,B for the NFETs is greater than that for the PFETs, which is mainly attributed to the S/D dopant diffusion into the PTS region. Phosphorus has a higher diffusivity than boron; therefore, more S/D dopant diffuses into the PTS region in NFETs than in PFETs [30]. Consequently, the NFETs are more sensitive to the ΔTIS,B in terms of Ioff. For the NFETs with TSD = 5 nm, SIoff,T, SIoff,M, and SIoff,B were 0.195, 0.209, and 2.34 nA/nm, respectively. SIoff,T and SIoff,M were almost identical regardless of the TSD, but SIoff,B increased by a factor of 22.5 when the TSD increased from 0 to 5 nm. This indicated that the S/D recess process variation slightly affects SIoff,T and SIoff,M but significantly affects SIoff,B. Thus, if the TSD variation is not perfectly eliminated, ΔTIS,B should be controlled below 1 nm, because devices with greater than 10 times in Ioff are not suitable for the intended system-on-chip applications.

Figure 3

Ioff of NSFETs according to ΔTIS with TSD = 0 and 5 nm.

The differences in the SIoff shown in Figure 3 can be explained using the Ioff-density profiles (Figure 4). In NSFETs with TSD = 0 nm, most carriers existed in the NS channels, and a few were in the PTS region owing to the heavily doped PTS. Furthermore, ΔTIS-induced Ioff density variations mainly arose in the NS channels next to the inner spacer with variations in the thickness. Thus, the top and middle inner spacers adjacent to the NS channels with high carrier concentrations exhibited larger changes in the Ioff density than the bottom inner spacer. Therefore, SIoff,T and SIoff,M are higher than SIoff,B for the NSFETs with TSD = 0 nm. By contrast, SIoff,B was the highest when the TSD was 5 nm. Figure 4b shows the Ioff density profiles for NFETs with different TIS,B in the case of TSD = 5 nm. As TIS,B increased, the off-state Ipt (Ipt,off) was not suppressed, resulting in a significant increase in Ioff, as shown in Figure 2. The Ioff density varied according to ΔTIS,B in the bottom NS and PTS regions but varied to a significantly larger extent in the PTS region. Specifically, the TSD variation significantly enhanced the effects of trpbt on Ioff, and the change in Ipt,off was a dominant factor in the SIoff,B increment. This is because the PTS region was only controlled by the bottom gate. Therefore, the bottom gate could not effectively control the PTS region far from the bottom gate. As a result, worse short-channel effects (SCEs) were observed in the PTS region than in the NS channel.

Figure 4

(a) Ioff density profiles of the NFETs with TSD = 0 and each ΔTIS equal to 2 nm. (b) Ioff density profiles of the NFETs with TSD = 5 nm for different values of ΔTIS,B.

Figure 5a shows the conduction band energy (Ec) diagrams of the source–PTS–drain in the NFETs, which were extracted under the off-state bias condition. As the TSD increased from 0 to 5 nm, the significant reduction in the energy barrier height (Φb) from 478 to 402 mV was caused by the larger amount of S/D dopant diffusion into the PTS region at a TSD of 5 nm. In NFETs with TSD = 0 nm, the Φb of the PTS region was sufficiently high to control Ipt,off regardless of ΔTIS,B (Figure 5b). Therefore, Ioff can be effectively controlled even with ΔTIS,B. However, if Φb is not sufficiently high, the additional Φb reduction due to ΔTIS,B can be a critical factor in inducing Ipt,off. An additional Φb reduction was observed when TIS,B increased, and the change in Φb by ΔTIS,B significantly contributed to the Ipt,off variation (Figure 3 and Figure 5c). Therefore, the bottom LG of trpbt, which is related to TIS,B, is important for suppressing SCEs in the PTS region. According to these results, SIoff,B is significantly affected by TSD. Thus, minimizing ΔTIS,B is more crucial when an over-etched S/D recess occurs.

Figure 5

(a) Energy band diagram of the source–PTS–drain in NFETs with TSD = 5 nm (solid line) and TSD = 0 nm (dashed line). The Ec of the PTS region with different TIS,B at (b) TSD = 0 and (c) TSD = 5 nm.

Figure 6 shows the relationship between the on-state current (Ion) and ΔTIS, and the slope indicates the Ion sensitivity (SIon). For the NFETs, the SIon,T and SIon,M are slightly higher than the SIon,B regardless of the TSD. By contrast, for the PFETs, the SIon,B varied significantly with respect to the TSD, leading to an increase in SIon,B by a factor of 1.9. Thus, an increase in ΔTIS,B can cause severe Ion variations when the TSD is not precisely controlled. The reason for the differences in the SIon is explained in Figure 7.

Figure 6

Ion of NSFETs having different ΔTIS with TSD = 5 nm (solid symbols) and TSD = 0 nm (open symbols).

Figure 7

(a) Parasitic resistance (Rsd) of NFETs with respect to the ΔTIS. (b) Ipt,on density of NSFETs with respect to the ΔTIS,B.

The Rsd sensitivity (SRsd) and on-state Ipt (Ipt,on)-density variations to the ΔTIS account for the differences in T/M/B SIon (Figure 7). Rsd was extracted using Y-function techniques, as described in [31]. Two main factors determine SIon: Rsd and inversion charges in the PTS region. Additionally, the major factors affecting SIon depend on the TSD. For both the NFETs and PFETs with TSD = 0 nm, SIon was mainly affected by the change in Rsd, which consisted of the series S/D epi resistance (Repi) and extension resistance (Rext). Repi did not change with respect to ΔTIS, but Rext did. Because SRsd varied proportionally to the number of NS channels adjacent to the inner spacer where ΔTIS occurred (Figure 7a), SIon,T and SIon,M were greater than SIon,B. However, the inversion charges in the PTS region significantly affected SIon when TSD was 5 nm. As the deep TSD caused a substantial current to flow through trpbt, the Ion contribution of the PTS region was no longer small. The inversion charges in the PTS region should also be considered (Figure 7b). For the NFETs, the Ipt,on density in trpbt decreased slightly as TIS,B increased, whereas the large decrease in Ipt,on was observed for the PFETs. This is because higher SCEs and Vth reductions were observed in the NFETs, as the large amounts of diffused S/D dopants reduced Φb (Figure 2b and Figure 5a). Therefore, in the NFETs, the Vth reduction of trpbt lowered the effects of the increase in Rsd, which was the dominant factor determining SIon,B. By contrast, in the PFETs, the Vth reduction of trpbt was small; thus, Ipt,on decreased significantly owing to the increase in the Rsd of trpbt. Consequently, SIon,B was the smallest for the NFETs, but for the PFETs, the TSD variation caused Ion to be most sensitive to ΔTIS,B.

Based on these results, we can provide two guidelines for controlling the DC performance variation, which depends on TSD. In the case of TSD = 0, precisely controlling TIS,T and TIS,M rather than TIS,B is effective for minimizing the variations in Ioff and Ion, as shown in Figure 3 and Figure 6. However, considering the TSD variation, it is necessary to focus on the bottom inner spacer, because a precisely controlled TIS,B, can considerably reduce the performance variation. Otherwise, the effects of trpbt on the DC performance become large as TIS,B increases, resulting in the worst case with the highest Ioff and lowest Ion in PFETs, which significantly diminishes the performance advantages of NSFETs.

The gate capacitance (Cgg) with respect to ΔTIS for NSFETs (TSD = 0) is shown in Figure 8, and Cgg is decomposed into the intrinsic capacitance (Cint) and parasitic capacitance (Cpara). Cpara was extracted under the off-state bias, and Cint was calculated by subtracting Cpara from Cgg under the on-state bias. As shown in Figure 8a, the differences in the Cgg sensitivity to T/M/B ΔTIS (SCgg) were small. However, the changes in Cint and Cpara for each ΔTIS did not have the same sensitivity. Cpara, which was determined by the fringing field between the gate and S/D, was affected by the TIS. Therefore, the sensitivity of Cpara to ΔTIS was almost identical among the T/M/B ΔTIS (Figure 8b). However, the sensitivity of Cint to ΔTIS,B was lower than those of ΔTIS,T and ΔTIS,M (Figure 8c). Although the inversion charge variations caused by ΔTIS,B mainly occurred in the bottom NS and PTS regions, the charge variations in the PTS region were smaller than those in the NS channels, leading to different AC sensitivities to the T/M/B ΔTIS. However, because the differences in the Cint sensitivity to the T/M/B ΔTIS were not large, it can be concluded that the overall performance sensitivity difference induced by each ΔTIS has greater effects on DC (Ioff, Ion) rather than the AC performance.

Figure 8

(a) Cgg, (b) Cpara, and (c) Cint for NFETs with respect to ΔTIS (TSD = 0). The capacitances were extracted at a frequency of 1 MHz.

4. Conclusions

The sensitivities of the DC/AC performance to the T/M/B ΔTIS in sub-3-nm node NSFETs were quantitatively investigated using a fully calibrated TCAD simulation. The DC performance sensitivities (Ioff, Ion) to the T/M/B ΔTIS differed. However, there were no significant differences in the AC sensitivities. One of the notable results was that ΔTIS, which varied the performance the most, was different according to the TSD variations. In NSFETs with TSD = 0 nm, SIoff,B was lower than SIoff,T and SIoff,M because the effects of ΔTIS,B were primarily observed in the bottom NS channel. However, trpbt was no longer negligible when the TSD was 5 nm. Thus, if the TSD variation is not controlled, NFETs (PFETs) have higher SIoff,B (SIon,B) because of the effects of trpbt. It can be concluded that the bottom inner spacer is the element with the most significant effect on the DC/AC performance. Hence, reducing ΔTIS,B is important for yield enhancement.