| Literature DB >> 35517775 |
Zepu Zhang1, Yijie Nie1, Weiwei Hua1, Jingxuan Xu1, Chaoyi Ban1, Fei Xiu1, Juqing Liu1.
Abstract
The facile synthesis of large-area coordination polymer membranes with controlled nanoscale thicknesses is critical towards their applications in information storage electronics. Here, we have reported a facile and substrate-independent interfacial synthesis method for preparing a large-area two-dimensional (2D) coordination polymer membrane at the air-liquid interface. The prepared high-quality 2D membrane could be transferred onto an indium tin oxide (ITO) substrate to construct a nonvolatile memory device, which showed reversible switching with a high ON/OFF current ratio of 103, good stability and a long retention time. Our discovery of resistive switching with nonvolatile bistability based on the substrate-independent growth of the 2D coordination polymer membrane holds significant promise for the development of solution-processable nonvolatile memory devices with a miniaturized device size. This journal is © The Royal Society of Chemistry.Entities:
Year: 2020 PMID: 35517775 PMCID: PMC9054294 DOI: 10.1039/d0ra02933e
Source DB: PubMed Journal: RSC Adv ISSN: 2046-2069 Impact factor: 4.036
Fig. 1(a) Illustration of the polymer membrane formation process at the interface. (b) Schematic of the polymer membrane at the air–liquid interface. (c) SEM images of the as-prepared membrane with a thickness of 300 nm.
Fig. 2(a) The orientation of the films for (i) out-of-plane XRD scan and (ii) in-plane XRD scan. (b) PXRD profiles of out-of-plane XRD and in-plane XRD of the polymer membrane. (c) N 1s core level spectra of the membrane. (d) FT-IR spectra of the membrane and the ligand; the inset is the structure of the polymer membrane.
Fig. 3(a) I–V curves of the Al/polymer membrane/ITO memory device. Inset: schematic of the device structure. (b) Retention ability test of the device at a reading voltage of −0.5 V in the HRS and LRS states. (c) The ON/OFF ratio of the device under different applied voltages. (d) Currents of the device in the ON and OFF states. (e) Statistic histograms of SET/RESET voltages. (f) The cell area dependence of resistances in HRS and LRS.
Fig. 4(a) Fitted I–V curves of the memory device at the SET process. (b) Fitted I–V curves of the memory device at the RESET process. (c–f) Transportation mechanisms of charge carriers from low conductive state to intermediate conductive state and further to high conductive state.