CMOS-compatible compute-in-memory accelerators based on integrated ferroelectric synaptic arrays for convolution neural networks.

Convolutional neural networks (CNNs) have gained much attention because they can provide superior complex image recognition through convolution operations. Convolution processes require repeated multiplication and accumulation operations, which are difficult tasks for conventional computing systems. Compute-in-memory (CIM) that uses parallel data processing is an ideal device structure for convolution operations. CIM based on two-terminal synaptic devices with a crossbar structure has been developed, but unwanted leakage current paths and the high-power consumption remain as the challenges. Here, we demonstrate integrated ferroelectric thin-film transistor (FeTFT) synaptic arrays that can provide efficient parallel programming and data processing for CNNs by the selective and accurate control of polarization in the ferroelectric layer. In addition, three-terminal FeTFTs can act as both nonvolatile memory and access device, which tackle issues from two-terminal devices. An integrated FeTFT synaptic array with parallel programming capabilities can perform convolution operations to extract image features with a high-recognition accuracy.

INTRODUCTION

Convolutional neural networks (CNNs) have been used in various applications, such as speech recognition and image classification (, ). CNNs can achieve superior performance in complex image recognition processes through convolution operations that use kernels as filters to extract features from images. However, convolution operations are time-consuming because they involve repeated multiplication and accumulation operations between the input data and the kernel weight. When CNNs are implemented in hardware based on the von Neumann architecture, drawbacks such as increased power consumption and limited data processing speeds arise because large amounts of data need to be transferred between the processing and memory units (, ). To overcome these limitations, compute-in-memory (CIM) has been suggested as alternative hardware for CNNs because it enables parallel data processing (–). In CIM, parallel data processing can be performed in a crossbar array structure using vector-matrix multiplication (VMM) based on Ohm’s law (for multiplication) and Kirchhoff’s law (for accumulation) (). For accurate VMM operation, synaptic devices are required, which can precisely adjust the conductance states via analog conductance modulation (, , ). In previous studies, several CIM devices with a crossbar structure have been demonstrated using two-terminal devices, such as phase-change and resistive-switching memories, as synaptic devices (–). However, when CIM is implemented using crossbar arrays based on two-terminal devices, there are issues such as cross-talk, sneak path current, and nonlinear current-voltage characteristics (–). The analog conductance modulation characteristics of two-terminal devices are usually achieved by controlling the current of devices during the programming process (–). However, in arrays consisting of two-terminal devices, it is difficult to control the current of selected devices during the programming process precisely because of current flowing through the unselected devices (, ). In addition, the current flowing through the unselected devices can affect the accuracy of read operation. Therefore, this issue can cause inaccurate conductance modulation in crossbar arrays based on two-terminal devices ().

Three-terminal devices have the potential to perform accurate conductance modulation in array structure because terminals for program and read operations are separated (, ). In an array composed of three-terminal devices, the program and read operations are not affected by the states of the unselected devices. Therefore, three-terminal devices, such as electrochemical transistors and charge-trapping transistors, have been investigated as synaptic devices (, , , , –). Electrochemical transistors exhibit linear weight updates and low-voltage operation (, ). However, the use of active ions (e.g., Li+) may be incompatible with complementary metal-oxide semiconductor (CMOS) device fabrication and integration (, ). Although charge-trapping transistors are based on mature technology for array integration, they require a high operation voltage and exhibit nonlinear weight update characteristics (, ). Among the available three-terminal synaptic devices, ferroelectric transistors based on zirconium-doped hafnium oxide (HfZrO) are advantageous because they have CMOS compatibility, fast operation speed, low operation voltages, and high scalability (–). In particular, the conductance of ferroelectric transistors can be precisely modulated by controlling the states of polarization in the ferroelectric layer (, , ). These properties can be used to implement kernel weights for convolution operations in ferroelectric transistor arrays. Thus, ferroelectric transistor arrays could be used as synaptic arrays for CIM.

In this study, we demonstrate integrated synaptic transistor arrays based on ferroelectric thin-film transistors (FeTFTs) composed of indium zinc oxide (IZO) and HfZrO. In these arrays, FeTFTs are used as synaptic devices. The conductance of the FeTFTs, which represents kernel weight, is linearly controlled by adjusting the states of polarization in the ferroelectric layer. In addition, column- and row-wise parallel programming operations are demonstrated in ferroelectric synaptic transistor arrays by the selective control of polarization switching with program-inhibit operations. Using these characteristics, ferroelectric synaptic transistor arrays are trained to implement kernel weights and perform convolution operations, which can be used to extract the features of input images. The four different kernels, which are realized in ferroelectric synaptic transistor arrays, can extract the features of an image with 64 × 64 pixels. In addition, neural network simulations based on the weight update characteristics of the ferroelectric synaptic transistor array exhibit an image recognition accuracy of 90.3%. The results of this study provide important information that can contribute to the development of CIM based on ferroelectric synaptic transistor arrays.

RESULTS

Parallel programming of a ferroelectric synaptic transistor array

The ferroelectric characteristics of the HfZrO were first confirmed using the ferroelectric capacitor with the molybdenum (Mo)/HfZrO/tungsten (W) structure (fig. S1). When the range of the voltage sweep increased from ±2 to ±6 V, the remnant polarization of the HfZrO increased. In a voltage sweep range of −6 to 6 V, a ferroelectric capacitor exhibited positive and negative remnant polarization of 15.1 and −14.1 μC/cm2, respectively. These results confirmed that HfZrO had ferroelectric characteristics and that its polarization characteristics could be adjusted by changing the amplitude of the applied voltages (, ). We fabricated synaptic transistor arrays by integrating FeTFTs with IZO and HfZrO (Fig. 1A). The fabrication process of the ferroelectric synaptic transistor array was CMOS compatible and could be achieved at a temperature under 400°C (fig. S2). First, gate lines (GLs) were formed by depositing W on the SiO2/Si substrate. Then, an HfZrO layer was deposited as the ferroelectric layer using atomic layer deposition (ALD). Next, a Mo layer was deposited to form the source lines (SLs), source electrodes, and drain electrodes. ALD was used to form an IZO layer, which acted as the channel layer. Then, the devices were annealed at 400°C to induce ferroelectricity in the HfZrO layer. Last, an interlayer dielectric was formed, and a Mo layer was deposited to act as the drain lines (DLs). These ferroelectric synaptic transistor arrays were composed of four GLs, four SLs, and nine DLs. In the ferroelectric synaptic transistor array, one column included nine FeTFTs, which had a bottom gate and bottom contact structure. Each column was connected to nine DLs, one GL, and one SL.

Fig. 1.

Ferroelectric synaptic transistor array and parallel programming operation.

(A) Optical image of the ferroelectric synaptic transistor array (left). Optical image and schematic illustration of an FeTFT in the array (right). (B) Equivalent circuit of the ferroelectric synaptic transistor array. The parallel (C) program and (D) read operation method. For parallel programming, four different programming patterns are used. During parallel programming, program pulses are applied to selected GLs, and selected DLs are set to 0 V. Program-inhibit pulses are applied to the unselected DLs and all SLs. During read operation, the states of the devices in the same column are confirmed by measuring the currents of the DLs. (E) Readout currents (unit of nA) of devices in the array after parallel programming operation for four different cases of programming patterns.

The switching characteristics of the FeTFTs were evaluated by measuring the device states after applying GL voltage (VGL) pulses with different amplitudes (fig. S3). The device states were confirmed by measuring the DL current (IDL) at a DL voltage (VDL) of 0.1 V, while sweeping VGL from 0 to −3.5 V. Before the measurements, the FeTFTs were erased by applying an erase pulse (−5 V, 10 ms) to the GL, while SL and DL were set to 0 V. Subsequently, program pulses with a width of 10 ms were applied to the GL. The amplitudes of the program pulses increased from 2.5 to 5 V in increments of 0.25 V. As the amplitudes of the pulses increased, the IDL-VGL curves gradually shifted in the negative direction, and the channel conductance increased. The switching characteristics of the FeTFTs were also investigated by applying program pulses with different amplitudes and widths (fig. S4). The pulse width required for conductance modulation decreased when the amplitude of the program pulse increased. These multilevel capabilities may originate from the partial polarization characteristics of the ferroelectric HfZrO layer, and these characteristics can be used to realize weights for kernel filters ().

In ferroelectric synaptic transistor arrays, FeTFTs in the same column share a single GL. Therefore, an unwanted program of unselected devices in the same column (called a program disturbance) can occur during programming of a selected device (, ). For selective and parallel programming in ferroelectric synaptic transistor arrays, these issues need to be solved. To demonstrate selective and parallel programming operation, we introduced a program-inhibit operation method. In the ferroelectric synaptic transistor array, 4 × 4 FeTFTs were used to demonstrate parallel programming in multiple columns and rows (Fig. 1B). Four different cases of programming patterns were used. In these cases, four devices were selected in the array. Before the parallel programming, FeTFTs in the array were erased by applying erase pulses (−5 V, 10 ms) to all GLs, while all SLs and DLs were set to 0 V. During the parallel programming of the selected devices, program pulses (4 V, 10 ms) were applied to the selected GLs, and the selected DLs were set to 0 V. In this operation, multiple GLs and DLs were selected to program the devices. Therefore, multiple devices in the arrays could be programmed in parallel. Program-inhibit pulses (2 V, 30 ms) were applied to the unselected DLs and all the SLs to prevent the program disturbance (Fig. 1C). The program-inhibit voltage reduces the difference between the voltages of the GL and the channel layer of the unselected FeTFT, and this can prevent polarization switching in the unselected devices (). After the parallel programming operation, the states of the devices in the same column could be confirmed simultaneously by measuring the current of the DLs, while a read voltage of 0.1 V was applied to the selected SL. All the DLs and GLs were set to 0 and −2 V, respectively (Fig. 1D) (). After the parallel programming, the current levels of the selected devices increased, and programming of the unselected devices was prevented (Fig. 1E). The program disturbance could be successfully prevented using program-inhibit pulses, which was confirmed by repeated program-inhibit operations (fig. S5). Using this parallel programming method, the FeTFTs in the ferroelectric synaptic transistor array could be simultaneously programmed, and program disturbance could be inhibited.

In addition, selective and parallel weight updates can be performed using the above operation methods. To demonstrate these updates, we selected two FeTFTs in the same column (Fig. 2A). During the potentiation and depression operations, multiple update pulses with incremental amplitudes and a width of 10 ms were applied to the selected GL, and the selected DLs were set to 0 V. The amplitudes of the potentiation and depression pulses increased from 2.7 to 3.96 V in a 20-mV step and from −2.7 to −3.96 V in a −20-mV step, respectively. Program-inhibit pulses with incremental amplitudes and a width of 30 ms were applied to the SL and unselected DLs. The amplitude of the program-inhibit pulses for potentiation and depression operations increased from 1.35 to 1.98 V in a 10-mV step and −1.35 to −1.98 V in a −10-mV step, respectively. The conductance of the devices was confirmed by measuring the current of the DLs, while a read voltage of 0.1 V was applied to the selected SL. All the DLs and GLs were set to 0 and −2 V, respectively. Using these methods, the selected devices were selectively and linearly updated. Disturbance from the weight update of neighboring synaptic devices was not observed (Fig. 2B). In addition, the cycle-to-cycle and device-to-device variation characteristics of FeTFTs were investigated. The endurance characteristics of a FeTFT were measured for 30 potentiation and depression cycles (Fig. 2C). During repeated pulse operations, degradation was not observed, and the cycle-to-cycle variation was about 1.3% (Fig. 2D). To evaluate the device-to-device variation, we measured the potentiation and depression characteristics of 36 FeTFTs in the array. The ferroelectric synaptic transistor array showed a device-to-device variation of about 3.7% (Fig. 2E). The small variations in the electrical properties of the ferroelectric synaptic transistor array are required for high accuracy of CIM ().

Fig. 2.

Weight update characteristics of the ferroelectric synaptic transistor array.

(A) Column-wise parallel weight update and read operation method. Two FeTFTs in the same row (C01 and C03) are selected for column-wise parallel weight update operations. During the potentiation and depression operations, multiple update pulses with incremental amplitudes were applied to the selected GL, and the selected DLs were set to 0 V. Program-inhibit pulses with incremental amplitudes were applied to the SL and unselected DLs. The conductance of the devices was confirmed by measuring the current of the DLs. (B) Column-wise parallel weight update characteristics of FeTFTs in the array. Weight update of selected FeTFTs (C01 and C03) was done in parallel, while the states of unselected FeTFTs (C02 and C04) remained. (C) Endurance characteristics of FeTFTs for 30 potentiation and depression cycles. (D) Cycle-to-cycle variation characteristics of 30 potentiation and depression cycles. (E) Device-to-device variation characteristics of potentiation and depression cycles of 36 devices.

With column-wise parallel update method, synaptic devices with different states are hard to be updated because it is difficult to apply the update pulse with different amplitudes to the devices in the same column. This issue can be solved by using row-wise parallel weight update methods. Devices in the same row do not share the same GL, thus update pulses with different amplitudes can be simultaneously applied to devices in the same row. Therefore, we demonstrated a row-wise parallel weight update for devices with different states. To demonstrate row-wise parallel weight update, we selected two FeTFTs in the same row (fig. S6A). During the potentiation and depression operations for each device, different amplitudes of potentiation and depression pulses based on the current device state were applied to the selected GLs, and the selected DLs were set to 0 V. Program-inhibit pulses were applied to the SL and unselected DLs. The conductance of the devices was confirmed by measuring the current of the SLs, while a read DL voltage of 0.1 V was applied to the selected DL. All the SLs and GLs were set to 0 and −2 V, respectively. Using these methods, the devices with different states were simultaneously and linearly updated. Disturbance from the weight update of synaptic devices in the same row was not observed (fig. S6B). Thus, the results showed that the parallel programming to different states could be achieved using column- and row-wise parallel update scheme.

In the ferroelectric synaptic transistor array, an incremental pulse scheme was used for the weight update. The use of an incremental pulse scheme can complicate the circuit design for the generation of pulses with different amplitudes and increase power consumption because of the additional steps for accessing the weight values (). When an incremental pulse scheme is used, the weight values need to be confirmed before the weight update to determine the amplitude of the update pulse. Thus, the time required for training can be increased when using incremental pulse scheme in FeTFT array. Further study is being done to reduce the training time in the FeTFT array structure. Although there are some issues associated with an incremental pulse scheme, the use of this scheme can produce highly linear weight update characteristics, which are essential requirements for CIM hardware with a high recognition accuracy because the weights of the synaptic devices should be precisely adjusted to the desired values (). In a ferroelectric synaptic transistor array, symmetric and linear weight update characteristics can be achieved by precisely controlling the state of polarization in the ferroelectric layer, which can be used to adjust the weights of the FeTFTs to the desired values. In addition, these linear weight update characteristics can be achieved in parallel weight update using the three-terminal structure of FeTFTs. These parallel weight updates can improve the efficiency of the weight update process as the weights of multiple devices can be updated simultaneously. These results indicate that the ferroelectric synaptic transistor array can be used to realize the efficient CIM hardware with a high accuracy.

Convolution operation in a ferroelectric synaptic transistor array

In convolution operations, the intensity value of each pixel, which represents the brightness of the pixel in the input image, is multiplied by the kernel weight (Fig. 3A). The output is the sum of the products of the intensity values of the input pixels and the kernel weights. Therefore, multiplication and accumulation operations are required for convolution operations. To perform convolution operations in the synaptic transistor array, the intensity values of pixels and kernel weights are converted into voltages and the conductance of the synaptic devices, respectively (). Multiplication of the intensity values of the input pixels by the kernel weights can be achieved using Ohm’s law, and the accumulation can be achieved using Kirchhoff’s law (, ). Thus, linear current-voltage characteristics are required for accurate convolution operations based on the VMM (, , , ). The FeTFTs exhibited linear current-voltage characteristics at multiple states between the erased and programmed states (fig. S7). The linearity of the current-voltage was defined as I-V linearity = [IDL at VDL (0.1 V)]/2[IDL at VDL (0.05 V)] (). The I-V linearity of the FeTFTs was about 0.95. These characteristics are important for realizing accurate convolution operation.

Fig. 3.

Demonstration of convolution operation using the ferroelectric synaptic transistor array.

(A) Convolution operation in a convolutional layer. The intensity value of each pixel in an input image is multiplied by the weight in the kernel. The output is the sum of the products of intensity values and kernel weights. (B) Input image with 6 × 6 pixels for convolution operations. The intensity values of 3 × 3 pixels in the input image are converted into voltages from 0 to 0.1 V, which are assigned to each DL in the ferroelectric synaptic transistor array. (C) Equivalent circuits of FeTFT array, including one column for positive weight and the other column for negative weight. I+ and I− represent the output currents of SLs of those columns with positive and negative weights, respectively. (D) Subtractor circuit composed of two op-amps for the differential readout between the output currents of the positive- and negative-weight columns. Reference (Rref) and normalization (Rnorm) resistance of 1 kilohm and 1 megohm were used for the first and second op-amps, respectively. Two op-amps are connected by using the other Rref of 1 kilohm. The output voltage (Voutput) of the subtractor circuit is measured at the output terminal of the second op-amp. (E) Output voltages (unit of V) of convolution operations using the ferroelectric synaptic transistor array for the input image. (F) Image feature extraction based on convolution operation using the ferroelectric synaptic transistor array for four different kernels. A grayscale Lena image with 64 × 64 pixels is used as the input image. Each pixel of the input image has an intensity value from 0 to 255, which is converted into a voltage from 0 to 0.1 V. Vertical edge, horizontal edge, mean, and sharpen kernels are used for image feature extraction.

To investigate the potential of ferroelectric synaptic transistor arrays for convolution operations, we performed convolution operations based on a vertical edge kernel for an input image with 6 × 6 pixels. To perform convolution operation, we converted the intensity values of 3 × 3 pixels in the input image into voltages from 0 to 0.1 V, which were assigned to each DL in the ferroelectric synaptic transistor array (Fig. 3B). To realize a kernel with 3 × 3 weights in a ferroelectric synaptic transistor array, we used two columns of the array because a differential pair was required to represent both the positive and negative weights in the kernel (Fig. 3C) (, , ). The channel conductance of the FeTFTs in two columns of the array was adjusted to the value required to realize the weights of the vertical edge kernel, which could extract features corresponding to the vertical edges of the input image (fig. S8). The first and second columns represented the positive- and negative-weight values in the kernel, respectively. Therefore, in a 9 × 2 array, a differential of weights could represent a kernel with 3 × 3 weights. For the weights of the kernel, precise conductance modulation characteristics are required to adjust the synaptic weight to the desired value (). In this respect, the analog weight update characteristics of FeTFTs are advantageous in synaptic devices used for convolution operations (). The FeTFT arrays were programmed to the desired values using the column-wise parallel programming method. When voltages that were converted from intensity values of 3 × 3 pixels were applied to DLs of the ferroelectric synaptic transistor array, the output currents of SLs in the columns with positive and negative weights represented the sum of the product of the channel conductance and VDL. During convolution operations, read GL voltages of −2 V were applied to all the GLs. For the differential readout between the output current of positive- and negative-weight columns, a subtractor circuit consisting of two operational amplifiers (op-amps) was used (Fig. 3D). The inverting input terminals of the first and second op-amps were connected to the SLs of the positive- and negative-weight columns, respectively. In this circuit, the differential readout between the output current of positive- and negative-weight columns was converted into the output voltage (Voutput) of the subtractor circuit (). A 1-kilohm reference resistance (Rref) was used for the first op-amp. A normalization resistance (Rnorm) of 1 megohm was used for the second op-amp. The output terminal of the first op-amp and the inverting input terminal of the second op-amp were connected using the other 1-kilohm Rref. The Voutput of the subtractor circuit was measured at the output terminal of the second op-amp. This represents the differential readout between the output currents of the positive- and negative-weight columns. The ratio between the differential readout and Voutput can be adjusted according to Rnorm in the second op-amp. For an input image with 6 × 6 pixels, convolution operation systems composed of ferroelectric synaptic transistor arrays and op-amps exhibited different Voutput values depending on the features of the image (Fig. 3E). The Voutput values of convolution operation using the ferroelectric synaptic transistor array exhibited a tendency similar to that of the expected output values shown in Fig. 3A, which confirmed that the ferroelectric synaptic transistor arrays could perform parallel data processing for convolution operations. These accurate convolution operations performed by the ferroelectric synaptic transistor array may be the result of integrated array structure, linear current-voltage behaviors, and analog conductance modulation characteristics of FeTFTs.

Ferroelectric synaptic transistor arrays are advantageous in energy consumption for the convolution operation because weight values of FeTFTs can be realized at a low conductance (~1 μS). When a pulse width of 10 ns is assumed for the convolution operation, the energy consumption of the ferroelectric synaptic transistor array for a single convolution operation based on a kernel with 3 × 3 weights is ~2 fJ [E = V2 × G × t × n = (0.1 V)2 × ~1 μS × 10 ns × 18], where E, t, and n stands for consumed energy, pulse width, and number of ferroelectric synapses, respectively (). These characteristics of ferroelectric synaptic transistor arrays have the potential for energy-efficient convolution operation. In addition, the low power consumption of convolution operation using ferroelectric synaptic transistor arrays can improve the energy efficiency of CNN. To evaluate the feasibility of convolution operations using ferroelectric synaptic transistor arrays for image processing, image feature extraction was performed using the Lena image (Fig. 3F) (, , ). For the image processing, four different kernels, including vertical edge, horizontal edge, mean, and sharpen, were used (fig. S9) (). To implement these four different kernels, the conductance of the FeTFTs in the 9 × 2 ferroelectric synaptic transistor array was adjusted to the desired values using the column-wise parallel programming method. To demonstrate the image feature extraction operation, a grayscale Lena image with 64 × 64 pixels was used as the input image. The intensity value of each pixel, which represents the brightness of the pixel in the input image, has a range from 0 to 255. The intensity of each pixel was converted into a voltage from 0 to 0.1 V. Then, the voltages that were converted from intensity values of 3 × 3 pixels in the Lena image were sequentially applied to the DLs in the ferroelectric synaptic transistor array and the total current of each column was summed, while all the GLs were set to −2 V. For the differential readout between currents of the positive- and negative-weight columns, a subtractor circuit composed of two op-amps was used. By repeating this process, the Lena image was processed for four different kernels. The Voutput values represented the features in the Lena image, depending on the types of kernels. These results indicate that ferroelectric synaptic transistor arrays can perform image processing for feature extraction.

Simulation of CNN based on ferroelectric synaptic transistor arrays

An eight-layer visual geometry group (VGG-8) network for the Canadian Institute for Advanced Research (CIFAR-10) dataset was simulated to investigate the potential of using ferroelectric synaptic transistor arrays as the hardware for CNNs (, ). The VGG-8 network was composed of six convolutional, three max pooling, and two fully connected layers (Fig. 4A). One max pooling layer was used for every two convolutional layers. The size of the input CIFAR-10 images was 32 × 32 × 3 pixels. For the convolutional layers, kernels with 3 × 3 weights were used. When CIFAR-10 images were processed by the first and second convolutional layers, the size of the feature maps was 32 × 32 × 128. After the third and fourth convolutional layer operations, feature maps with a size of 16 × 16 × 256 were obtained. Then, feature maps with a size of 8 × 8 × 512 were acquired by the fifth and sixth convolutional layer operations. Feature maps with a size of 4 × 4 × 512 were obtained after max pooling process. The feature maps were connected to the fully connected layers (). The convolutional and fully connected layers were used to extract features in the images and classify the images, respectively. The simulation tool used in this work is based on the identical pulse scheme to program the synapse array (). Further simulation studies need to be done to reflect the exact operation scheme and processes including nonidentical pulse operations.

Fig. 4.

CNN based on ferroelectric synaptic transistor arrays.

(A) Schematic illustration of VGG-8 network for the CIFAR-10 dataset. The VGG-8 network is composed of six convolutional, three max pooling, and two fully connected layers. The convolutional and fully connected layers are used to extract features in the images and classify the images, respectively. (B) Weight update characteristics of FeTFTs. For the linear weight update characteristics, incremental pulses (potentiation, 2.7 to 3.96 V with a 20-mV step; depression, −2.7 to −3.96 V with a −20-mV step) are used. (C) Comparison of simulated accuracies of VGG-8 network based on ferroelectric synaptic transistor arrays (blue circles and line) and on ideal devices (green squares and line).

To investigate the synaptic characteristics of FeTFTs, we measured the potentiation and depression characteristics by using an incremental pulse scheme (potentiation, 2.7 to 3.96 V with a 20-mV step; depression, −2.7 to −3.96 V with a −20-mV step). The linearity of weight updates represents the linearity of the curve between the conductance of the FeTFTs and the number of pulses (). The linearity of the weight update was evaluated using the following equations (, )where P, Gpot, and Gdep are the number of pulses and conductance after potentiation and depression, respectively. Pmax is the maximum number of pulses. Gmax and Gmin are the maximum and minimum conductance, respectively. Apot and Adep represent the linearity of the potentiation and depression characteristics, respectively (, ). In potentiation and depression operations, the FeTFTs showed 64-level conductance states, a Gmax/Gmin of 33.1, and a high linearity (Apot = 0.8139; Adep = 1.1464) (Fig. 4B). The low Gmax of FeTFTs in the weight update characteristics can be an advantage in the implementation of large arrays. With the high Gmax of synaptic devices, the current sum of the synapses may exceed the wire capacity of the arrays, which can lead to a reduction in the read accuracy (). For an efficient CIM array, Gmax needs to be lower than 10 μS (, ). In addition, the small cycle-to-cycle and device-to-device conductance variation of the ferroelectric synaptic transistor array are desired characteristics for CIM (Fig. 2, D and E) ().

The VGG-8 network was simulated using the synaptic characteristics of the ferroelectric synaptic transistor array, including the linearity of weight updates, the number of conductance states, Gmax/Gmin, the cycle-to-cycle variation, and the device-to-device variation characteristics. In simulations, the VGG-8 network based on a ferroelectric synaptic transistor array achieved 90.3% accuracy for 100 training epochs, which was comparable to the accuracy of 91.0% that the VGG-8 network based on ideal synaptic devices achieved (Fig. 4C) (, ). The high accuracy of the VGG-8 network based on a ferroelectric synaptic transistor array could be achieved because of weight update characteristics of the FeTFTs, such as high linearity (Apot = 0.8139; Adep = 1.1464), 64-level conductance states, Gmax/Gmin of 33.1, and small variation characteristics. In addition, the potentiation and depression characteristics with low conductance variation resulted in a high recognition accuracy of 91% for CIFAR-10 images with VGG-8 network using off-chip training method (). The change in the conductance of synaptic devices after training can cause the degradation of the accuracy (). Therefore, the retention characteristics of FeTFTs in different conductance states were also evaluated. The average change in the conductance of the FeTFTs was about 4.1%, and no overlap between the states was observed for 10,000 s (fig. S10). The stable retention characteristics of the FeTFTs can be advantageous for maintaining accuracy (). The simulation of a VGG-8 network confirmed that ferroelectric synaptic transistor arrays could be used as the effective neuromorphic hardware for CNNs.

DISCUSSION

In summary, we integrated FeTFTs based on IZO oxide semiconductors and ferroelectric HfZrO to investigate the potential of the ferroelectric synaptic transistor array for use in CIM applications. To implement the weight update characteristics, we controlled the conductance of the FeTFTs by adjusting the polarization of the ferroelectric layer. In ferroelectric synaptic transistor arrays, column- and row-wise parallel programming methods were experimentally demonstrated by the selective control of the polarization switching using program-inhibit operations. Kernel weights for convolution operations were realized in the ferroelectric synaptic transistor arrays using parallel weight update processes. The FeTFTs exhibited linear current-voltage behavior and weight update characteristics, which were essential for synaptic devices used for convolution operations. Accurate convolution operations were demonstrated in the ferroelectric synaptic transistor arrays using the kernel weights in the array. These convolution operations based on ferroelectric synaptic transistor arrays enabled the extraction of the features in an input image with 64 × 64 pixels. To further investigate the potential of the ferroelectric synaptic transistor arrays as CNNs for CIM, we simulated the CNNs using the characteristics of the ferroelectric synaptic transistor arrays. In simulations based on the weight update characteristics of the ferroelectric synaptic transistor arrays, the CNNs achieved an image recognition accuracy of 90.3% for a CIFAR-10 dataset. These results suggest that ferroelectric synaptic transistor arrays based on IZO oxide semiconductors and ferroelectric HfZrO have the potential to be used as neuromorphic hardware for CNNs.

MATERIALS AND METHODS

Materials

Hf[N(C2H5)CH3]4 [tetrakis(ethylmethylamido)hafnium (TEMAH)] and Zr[N(C2H5)CH3]4 [tetrakis(ethylmethylamido)zirconium (TEMAZ)] were purchased from UP Chemical, Korea. C10H28NSi2In4 [bis(trimethylsilyl)amidodiethyl indium (INCA-1)] and Zn(C2H5)2 [diethylzinc (DEZ)] were purchased from iChems, Korea. Si wafers with 100-nm-thick thermally grown SiO2 were used as substrates.

Device fabrication

The ferroelectric synaptic transistor arrays were fabricated on the SiO2/Si substrate. The photolithography was performed using a mask aligner (MDA-400LJ, Midas System). First, the SiO2/Si substrate was cleaned in acetone, ethanol, and deionized water for 15 min each. W GLs were deposited on the substrate via DC sputtering. The W layer was patterned using the lift-off method. Then, a 24-nm-thick HfZrO layer was deposited using the ALD by alternating the ALD cycles of HfO2 and ZrO2 at 280°C. For the ALD process, TEMAH, TEMAZ, and ozone were used as the Hf precursor, Zr precursor, and oxygen source, respectively. Next, Mo SLs and drain electrodes were deposited using the electron beam evaporator. The Mo layer was patterned using the lift-off method. A 10-nm-thick IZO film was deposited at 150°C using INCA-1, DEZ, and ozone as the indium precursor, zinc precursor, and oxygen source, respectively. The IZO layer was patterned using a combination of lithography and wet etching. The channel length and width were 10 and 50 μm, respectively. Then, the devices were annealed at 400°C for 10 min in an N2 environment. A 15-nm-thick HfO2 layer was deposited as an interlayer dielectric using the ALD. The etching process was done to open the contacts for the SLs, GLs, and drain electrodes. Mo was then deposited and patterned for the formation of DLs using the same method described above.

Characterizations

All the characteristics were measured under ambient conditions and at room temperature. The electrical properties of the ferroelectric synaptic transistor array were measured using a semiconductor parameter analyzer (4200A-SCS, Keithley Instruments) and a switching matrix (707B, Keithley Instruments). The polarization-voltage curves were measured using a pulse measurement unit (4225-PMU, Keithley Instruments). The polarization-voltage characteristics of the ferroelectric capacitor with a Mo/HfZrO/W structure were measured after 105 bipolar pulse cycles using voltage pulses with an amplitude of 5 V and a width of 10 μs. The thicknesses of the HfZrO and IZO were measured using an atomic force microscope (NX10, Park Systems). VGG-8 network simulations were performed with a Linux system using C++ code and a Python wrapper (). For recognition accuracy simulations, the learning rate was 1 for the initial 50 epochs and changed to 0.125 after 50 epochs. In this simulation, the characteristics of the ferroelectric synaptic transistor array, including Gmax/Gmin, linearity, the number of states, cycle-to-cycle variation, and device-to-device variation, were considered. For the simulation of the VGG-8 network based on ideal synaptic devices, ideal synaptic characteristics (including a perfectly linear conductance modulation of Gmax/Gmin = 100 and 100 conductance states) were used ().