Polarity Control in Ge Nanowires by Electronic Surface Doping.

The performance of nanoscale electronic and photonic devices critically depends on the size and geometry and may significantly differ from those of their bulk counterparts. Along with confinement effects, the inherently high surface-to-volume ratio of nanostructures causes their properties to strongly depend on the surface. With a high and almost symmetric electron and hole mobility, Ge is considered to be a key material extending device performances beyond the limits imposed by miniaturization. Nevertheless, the deleterious effects of charge trapping are still a severe limiting factor for applications of Ge-based nanoscale devices. In this work, we show exemplarily for Ge nanowires that controlling the surface trap population by electrostatic gating can be utilized for effective surface doping. The reproducible transition from hole- to electron-dominated transport is clearly demonstrated by the observation of electron-driven negative differential resistance and provides a significant step towards a better understanding of charge-trapping-induced transport in Ge nanostructures.

Introduction

Over the last few decades, following Moore’s law,[1] the continuous down-scaling of the Si-based, planar integrated circuit technology has been the main driving force to reduce size, power consumption, and cost of ultrascaled integrated circuits. However, the implications of short-channel effects[2] forced a shift of research efforts towards the integration of new materials, processes, and device architectures.[3] In this context, Ge is particularly interesting due to its high and almost symmetric electron and hole mobilities,[4] larger exciton Bohr radius,[5] and much longer scattering mean free paths,[6] compared to Si.[7] Consequently, Ge is considered as the key material in a More-than-Moore approach extending device performances beyond the limits imposed by miniaturization.[8,9] Low-dimensional Ge structures such as nanomembranes[10,11] and vapor–liquid–solid (VLS)[12] grown nanowires (NWs)[13,14] have gained particular attention due to their superior electrical[5,15,16] and optical[17−19] properties. Aside from physical advantages, NWs are also of foremost interest to the semiconductor industry because their dimensions are of a technologically relevant scale and inroads have already been made towards incorporating them into mature Si platform technology.[20−22] However, a serious concern regarding the practical use of NWs are the deleterious effects related to charge-carrier trapping, which are associated with the inherently high surface-to-volume ratio of quasi-one-dimensional (1D) structures.[16] According to the pioneering work of Hanrath et al.[23] and Zhang et al.,[24] Ge NWs have been proven to be an eligible platform for studying the influence of surface trap states on electronic transport phenomena.

In this work, we systematically study electronic surface doping and demonstrate polarity control in nominally intrinsic Ge NWs. For the electron-dominated transport regime, we reveal negative differential resistance (NDR), with potential applications in fast switching logic circuits, static memory cells, or high-frequency oscillators.[25]

Methods

Synthesis of Ge NWs

The used Ge NWs were grown on a Si (111) substrate using a VLS process with germane (GeH4, 2% diluted in He) as a precursor and a 2 nm thick sputtered Au layer as the 1D growth promoting catalyst. The actual growth was performed using a homebuilt low-pressure hot-wall chemical vapor deposition chamber at a total pressure of 50 mbar and a gas flow of 100 sccm for both the precursor gas and H2 as the carrier gas. After stabilizing the pressure and precursor gas flow, the temperature was ramped up at a rate of 60 °C/min to the target temperature of 340 °C. The rather high growth temperature ensures a uniform diameter and excellent NW epitaxy. After a 10 min nucleation phase, the temperature was lowered to 300 °C. A typical growth duration of 60 min results in 8 μm long NWs with uniform diameters of about 30 nm. Subsequent to the growth, the NWs were uniformly coated with a 20 nm thick Al2O3-shell[26] by atomic layer deposition at a temperature of 200 °C.

Device Fabrication

The starting materials were VLS-grown Ge NWs with diameters of about 30 nm coated with 20 nm thick Al2O3-shell by atomic layer deposition. The passivated Ge NWs were drop casted onto a 100 nm thick thermally grown SiO2 layer atop of a 500 μm thick p-doped Si substrate acting as a common back gate. The doping concentration of the Si substrate was 1020 cm–3, resulting in a resistivity of 0.0005–0.0008 Ωcm. The Ge NWs were contacted by polycrystalline Al pads fabricated by electron beam lithography, 100 nm Al sputter deposition, and lift-off techniques. A successive thermally induced exchange reaction by rapid thermal annealing at a temperature of T = 624 K in a forming gas atmosphere initiates the substitution of Ge by Al.[27−29] Facilitating this heterostructure formation scheme allows the integration of single-crystalline monolithic Al–Ge-Al NW heterostructures with tunable channel lengths in a back-gated field-effect transistor (FET) architecture.

Electrical Characterization

The electrical measurements at room temperature under ambient conditions were performed using a combination of a semiconductor analyzer (HP 4156B) and a probe station. To minimize the influence of ambient light as well as electromagnetic fields, the probe station is placed in a dark box. The low-temperature measurements were performed in vacuum at a background pressure of approximately 2.5 × 10–5 mbar using a liquid nitrogen flow cryostat (Cryo Industries CRC-102) and a semiconductor analyzer (Keysight B1500A).

Results and Discussion

To investigate the electrical properties, VLS-grown Ge NWs with diameters of 30 nm were integrated in back-gated field-effect transistors (FETs). For device fabrication, a thermally induced exchange reaction between the NWs and Al contact pads is used to achieve Ge segments contacted by self-aligned, single-crystalline Al NW leads[30] with atomically sharp heterojunctions (see Figure a).[27] The particular monolithic and quasi-1D Al contact geometry prevents screening of the gate electric field, which is a common problem of nanoscale back-gated FETs with extended source/drain contacts.[31] Details regarding the fabrication process as well as high-resolution transmission electron microscopy and energy dispersive X-ray spectroscopy investigations that prove the composition and perfect crystallinity of the NW heterostructure can be found in the work of Kral et al.[27] and El Hajraoui et al.[28] According to the large surface-to-volume ratio, adsorbates and surface states have significant impact on the electrical characteristics of NW-based devices.[24,32] Consequently, to ensure reliable and reproducible electrical measurements, the NWs were enwrapped in a protective 20 nm thick ALD-grown Al2O3-shell (see schematic in Figure a).

Figure 1

(a) Schematic and SEM image of an Al–Ge–Al NW heterostructure embedded in a back-gated FET architecture. The length and diameter of the actual NW are L = 1940 nm and d = 30 nm, respectively. A cross-section of the Ge channel enwrapped in a 20 nm Al2O3-shell is schematically shown in the upper right corner. (b) Transfer characteristics of a Ge NW FET device at a bias of VS = 0.1 V recorded at T = 300 K (black and green) and T = 80 K (blue) for gate voltage sweeping rates of 0.25 and 2.5 V/s, denoted slow and fast sweeping, respectively. The arrows indicate the gate voltage sweeping direction.

First, basic transfer characteristic measurements were conducted to determine the modulation capability of the charge-carrier type and concentration in the NWs. Figure b shows typical transfer characteristics of a FET device with a Ge channel length of L = 1940 nm recorded with a rather slow gate voltage sweeping rate of 0.25 V/s at T = 300 K (black) and 80 K (blue).

At room temperature, the nominally intrinsic Ge NW exhibits ambipolar behavior, with hole accumulation at negative gate voltages and moderate inversion at VG > 7 V, which is commonly observed for intrinsic semiconductor NWs.[14] Surface doping,[33] due to acceptor-like traps, results in a shift of the energy band structure throughout the whole NW, causing p-type behavior in nominally intrinsic Ge NWs.[23,24] Furthermore, the transfer characteristic measured at T = 300 K reveals an ION/IOFF ratio of about 104 and distinct hysteresis effects.

In a simplified model (i.e., ohmic contacts and no band bending across the NW), one can assume that the conductivity at the minimum of the transfer characteristic corresponds to the conductivity of an intrinsic semiconductor (Fermi level at mid-gap) with the number of free electrons and holes equal to the intrinsic carrier density n. Using σ = e(nμn + pμp) and assuming simplified equal mobilities of electrons and holes, the average carrier mobility in the channel can be calculated according to . For the actual device with σ = 2.37 mS/cm, the calculated value of μ = 370 cm2/(V s), which is in good agreement with a former work on similar Ge NWs.[24] The overall lower mobility compared to bulk Ge is mainly attributed to pronounced surface scattering in thin NWs.[34,35]

Furthermore, we observed a pronounced hysteresis with the current to be not only dependent on VG but also the gate voltage sweeping direction and rate affecting the population of trap states in different ways.[23] The surface of Ge NWs with typical interface trap densities of 1013–1014 /(eV cm2),[24] up to three orders of magnitude higher compared to planar Ge structures, corresponding to roughly 0.2–2% of the surface atoms,[36] provide a large reservoir of such trap states, which act as a highly efficient local gate.[18] Considering the Ge NW device shown in Figure a, a maximum of 20 000 traps are involved in determining the device behavior. With time constants in the range from microseconds to several minutes for interface and oxide states respectively,[37] one cannot avoid hysteresis effects for dynamic measurements of Ge NW FETs.[14] However, as exemplarily shown in Figure b, upon increasing the sweeping rate from 0.25 V/s (black) to 2.5 V/s (green), the hysteresis is significantly reduced. As the trapping and detrapping of electrons is a kinetically limited process,[23] the time constants significantly increase at lower temperatures. Thus, measuring the transfer characteristic with a slow gate voltage sweeping rate of 0.25 V/s but at T = 80 K, leads also to a notable reduction of the hysteresis (blue curve in Figure b). The remarkable high ION/IOFF ratio of 107 is a result of the steeper Fermi distribution at lower temperatures,[4] and as shown below an overall reduced shielding of the electrostatic gate by the traps.

Figure shows the transient response of the Ge NW device at room temperature and T = 80 K when the gate voltage is abruptly switched from VG = −15 to 15 V. At room temperature and a gate voltage of VG = −15 V, a moderate bias voltage of VS = 0.1 V induces an instantaneous hole-dominated current of about IS = 400 nA (t = 0 min). Over a timespan of more than 60 min, the current decreases continuously by about 4 orders of magnitude, approaching a steady-state value of approximately 10 pA. At this point (t = 70 min), the gate voltage is abruptly switched to VG = 15 V, which according to the transfer characteristic in Figure , causes a polarity change and a sudden current increase to IS = 200 pA. This electron-driven current progresses nonmonotonically over time, with the minimum lower than the steady state at VG = −15 V.

Figure 2

Transient response of a Ge NW FET device for a fixed bias voltage of VS = 0.1 V and abrupt changes in the gate voltage measured at T = 300 K (black) and T = 80 K (blue). The green shaded region marks the electron-dominated transport regime. The length and diameter of the actual NW is L = 920 nm and d = 30 nm, respectively.

In contrast, if the same measurement is conducted at T = 80 K, no such transient behavior was observed. A negative gate voltage of VG = −15 V provokes an instantaneous current of IS = 78 nA (t = 0 min), which remains perfectly stable over time. The abrupt switching of the gate voltage to VG = 15 V (t = 70 min) results in an immediate drop of IS below the noise level of our measurement setup.

To explain the progress of IS over time, a model is proposed in which the transient behavior results from the gate-controlled redistribution of charged surface traps. The schematics in Figure illustrates the combined effects of the gate voltage and thereof controlled surface trap population on the band structure of an intrinsic Ge NW. At VG = 0 V and under equilibrium conditions, the low energetic traps below the Fermi level are filled up with electrons, while those above remain empty. (i) These charged traps close to the FET channel act as an effective negative gate (further denoted as local gate), inducing band bending and the common p-type behavior of nominally intrinsic Ge NWs.[23,38] Upon applying a negative gate voltage, the Fermi level shifts towards the valence band, inducing instantaneous hole accumulation (ii) and thus an abrupt increase of IS as shown in Figure at t = 0. According to the lowered Fermi level, filled traps start to be discharged and the local gate becomes less negative, resulting in reduced band bending. As the time constants of surface states in Ge can be extremely long,[37] the current decreases continuously for more than 60 min before a steady state (iii) is reached. In contrast, by applying a positive gate voltage of VG = 15 V, the Fermi level shifts towards the conduction band inducing channel inversion i.e., electron-dominated transport at the surface (iv). As there are now empty traps below the Fermi energy, they start filling up with electrons and the local gate becomes more negative counteracting the positive back gate. This continues until an equilibrium is reached and a similar band bending to that for VG = 0 V is obtained, but now with a higher number of filled traps (v). This very effective negative local gate overcompensates the positive back gate and after a short period of electron-dominated transport, marked by the green dashed area in Figure , the mechanism changes back to hole-dominated electrical transport.

Figure 3

Cross-sectional band structure of a Ge NW device to illustrate the transient behavior of the gate-controlled redistribution of charged surface traps: (i) Ge NW at VG = 0 V in equilibrium. (ii) Applying a negative gate voltage lowers the Fermi level, which results in the discharging of the surface traps. (iii) Equilibrium is reached with VG = −15 V and fewer traps are filled. (iv) Applying a positive gate voltage lifts the Fermi level and results in downward band bending and thus inversion at the surface. (v) The continuous filling of traps causes the NW to reach equilibrium again with a higher number of traps filled.

The ability to change the polarity of current transport via electronic surface doping will now be strikingly demonstrated by inducing NDR in the Ge NW device. For common n-doped Ge, NDR can be explained by the transferred electron effect following the Ridley–Watkins–Hilsum theory.[39] At sufficiently high electric fields, electrons from the energetically favorable conduction band valley, characterized by a low effective mass, are transferred to a heavy mass valley nearby.[40] Although the Γ-point minimum in Ge is energetically closer to the L-point minimum, the coupling constant between ⟨111⟩ and ⟨000⟩ minima is significantly lower than that between ⟨111⟩ and ⟨100⟩ minima.[41] Consequently, as schematically illustrated in the inset of Figure a, the transferred electron effect in Ge applies for the L-point and Δ-point minima of the ⟨111⟩ and ⟨100⟩ subbands of the conduction band with the respective effective masses of m* = 0.082m0 and m*Δ, = 0.288m0.

Figure 4

I/V curves of the Ge NW device with L = 920 nm and d = 30 nm measured at VG = 15 V in intervals of 1 min. Prior to the measurements, the traps were depleted at VG = −15 V for 60 min. (a) At T = 300 K, clear indications of NDR are visible during the first 4 measurements where the predominant transport mechanism is n-type. After about 5 min, when the polarity has changed back to hole-dominated electrical transport, the NDR effect disappears completely. The inset shows the band diagram of Ge with the electric field induced electron transfer from the ⟨111⟩ valley into the ⟨100⟩ valley. The polarity can be conserved by cooling down the previously depleted Ge NW device for 60 min at VG = −15 V. (b) Upon abruptly switching the gate voltage at T = 80 K to VG = 15 V, the device remains in the hole-driven transport regime resulting in a linear I/V characteristic. (c) After the initial trap depletion procedure (VG = −15 V for 60 min), the device was cooled down to T = 150 K and the gate voltage was abruptly changed to VG = 15 V to initiate n-type behavior. A subsequent cooldown to T = 80 K conserved the electron-dominated transport.

To induce NDR in the intrinsic Ge NWs, we forced the device into the electron-dominated transport regime (green shaded area in Figure ). After depleting the traps at VG = −15 V for 60 min, the gate was switched to VG = 15 V and I/V characteristics were measured in intervals of 1 min (Figure a). For the first measurement, where a high electron density in the inverted channel dominates the transport, unambiguous signatures of NDR were observed with a maximum peak-to-valley ratio (PVR) of about 10. For the successive measurements, the PVR decreases gradually as traps are continuously filled and thus less electrons contribute to the transport in the channel. Finally, after about 5 min, when the polarity is changed back to hole-dominated electrical transport, the NDR effect disappears completely.

As already demonstrated, at T = 80 K, a redistribution of traps by the means of electrostatic gating is kinetically blocked.[18,23] Consequently, it should be possible to freeze-in the transport regime based on the polarity of the device set at room temperature. Thus, by cooling down the Ge NW device, which was previously depleted for 60 min at VG = −15 V, one can conserve the polarity. Thus, when the gate voltage at T = 80 K is abruptly switched to VG = 15 V, the device remains in the hole-driven transport regime, resulting in the linear I/V characteristic shown in Figure b.

Setting up a stable electron-dominated transport required a slightly more complex process. After the initial trap depletion procedure (VG = – 15 V for 60 min), the device was cooled down to T = 150 K, where it was still possible to induce redistribution of traps by electrostatic gating. Next, the gate voltage was abruptly changed to VG = 15 V to initiate n-type behavior (green shaded area of Figure ). Subsequently, the device was cooled down to T = 80 K as quickly as possible freezing-in the electron-dominated transport. In contrast to the room temperature measurements shown in Figure a, it was now possible to reproducibly measure a stable NDR over minutes with a constant PVR of 21 (see Figure c).

Finally, we want to stress once again that both a large number of surface traps due to the large surface-to-volume ratio as well as contact issues common for nanoscale structures are among the most severe issues of Ge NW-based devices. Hence, a combination of a protective Al2O3-shell and reliable single-crystalline Al contacts was required to enable systematic analysis of the complex transient behavior of Ge NWs. Our findings are based on the evaluation of the electrical data of more than ten similar passivated Al–Ge–Al NW heterostructure devices. Beside some minor device-to-device variations, we qualitatively found the same behavior for all investigated Ge NW-based devices.

Conclusions

We have thoroughly analyzed the influence of surface trap states on the electrical transport properties of intrinsic Ge NW. Controlling the trap population by electrostatic gating, we demonstrated the potential of effective surface doping to cause a transition of charge transport from hole- to electron-driven, enabling NDR in intrinsic Ge. Importantly, the electrostatic control of surface states may enable to avoid the charge trapping related hysteresis effect that is commonly considered parasitic for nanoelectronics and even introduces new functionalities based on polarity control. Consequently, our investigations provide a framework for utilizing surface trapping related transport phenomena in Ge nanostructures, which could be a significant step towards the development of future device concepts for post-Si nanoelectronic and nanophotonic devices.