Dielectric Properties and Ion Transport in Layered MoS2 Grown by Vapor-Phase Sulfurization for Potential Applications in Nanoelectronics.

Electronic and dielectric properties of vapor-phase grown MoS2 have been investigated in metal/MoS2/silicon capacitor structures by capacitance-voltage and conductance-voltage techniques. Analytical methods confirm the MoS2 layered structure, the presence of interfacial silicon oxide (SiO x ) and the composition of the films. Electrical characteristics in combination with theoretical considerations quantify the concentration of electron states at the interface between Si and a 2.5-3 nm thick silicon oxide interlayer between Si and MoS2. Measurements under electric field stress indicate the existence of mobile ions in MoS2 that interact with interface states. On the basis of time-of-flight secondary ion mass spectrometry, we propose OH- ions as probable candidates responsible for the observations. The dielectric constant of the vapor-phase grown MoS2 extracted from CV measurements at 100 kHz is 2.6 to 2.9. The present study advances the understanding of defects and interface states in MoS2. It also indicates opportunities for ion-based plasticity in 2D material devices for neuromorphic computing applications.

Introduction

Transition metal dichalcogenides (TMDs) are among a large family of two-dimensional (2D) layered materials. They are generically described by the formula MX2, where M represents a transition metal such as molybdenum (Mo), tungsten (W), niobium (Nb) and others, and X stands for a chalcogen element, that is, sulfur (S), selenium (Se), or tellurium (Te).[1,2] Bulk TMDs are formed from vertically stacked 2D-layers that are held together by van der Waals forces, typically at an interlayer spacing of less than 1 nm. The electronic properties of TMDs range from semiconducting to superconducting, and include direct and indirect energy band gaps that depend on the number of layers.[1] Molybdenum disulfide (MoS2) is a semiconducting TMD material with a band gap ranging from 1.3 eV in bulk to 1.88 eV as a monolayer.[1,3] Appealing properties of single- and multilayer MoS2 have made the material a potential candidate for applications in nanoelectronics, optoelectronics and neuromorphic computing.[4−13] Interest for such applications of 2D materials is generally not limited to devices made from single atomic layers, but rather include multiple 2D layers and heterostructures thereof. Most of the early stage research on MoS2 has been conducted on small flakes obtained through mechanical exfoliation[14] or chemical exfoliation.[15,16] Although these techniques can yield high quality MoS2, they are not suitable for large scale applications as they are limited to small flakes.[17] More recently, CVD growth from gaseous precursors and thermal conversion of metal films (vapor-phase sulfurization) have been proposed as scalable methods for MoS2 growth.[18−22] Here, the latter technique has been used to grow large area MoS2 directly on silicon (Si) substrates.

Most of the research on electronic devices based on single- and few-layer MoS2 has focused on lateral transport properties of MoS2. In this work, we investigate layered MoS2 on Si substrates with respect to its dielectric properties perpendicular to the substrate, for a potential application as a dielectric barrier material in vertical heterostructure devices, such as graphene and 2D materials-based hot electron transistors (HETs), which are potential devices for high speed electronics.[23−27] The small band gap of MoS2 compared to available oxides,[1,3] and its low band offset with respect to silicon (Si)[1,3,28] makes it a good candidate for efficient emission barriers in HETs.[29] In combination with an ultrathin dielectric layer, MoS2 could also serve in a bilayer tunnel barrier configuration, which has been shown to enhance HET on-current levels.[30] In this context, it is essential to understand the electronic and dielectric properties of MoS2 as a barrier material. We have thus investigated capacitors, with MoS2 as the dielectric, through capacitance–voltage (C–V) and conductance–voltage (G–V) measurements.

Results and Discussion

The device fabrication process flow and the associated MoS2 synthesis procedure are illustrated with schematics shown in Figure a and 1b, respectively. An optical micrograph of one device can be found in Figure c. The MoS2 films were characterized by Raman spectroscopy after growth. The resulting Raman spectrum (Figure a) corresponds to the 2H MoS2 phase and shows the two prominent peaks (E2g1 and A1g), indicating the formation of crystalline MoS2.[31,32] The E2g1 peak is attributed to the in-plane vibrations of Mo and S atoms, while the A1g peak signifies the out-of-plane vibrations of S atoms.[32] Cross-sectional TEM investigations have been employed to visualize the layer sequence pertained in the metal–semiconductor–semiconductor (MSS) structure and the associated interfaces. Figure b reveals a clearly layered structure of the MoS2 film, which is nanocrystalline in nature and where most of the layers are oriented nearly vertical with respect to the Si face. Such vertically aligned layers are commonly observed in thick MoS2 and other TMD films grown by vapor-phase sulfurization technique.[33−35] The TEM images further show a ∼2.5–3 nm thick amorphous SiOX interfacial layer (IL) between Si and MoS2, which is consistent with earlier reports involving MoS2 growth on Si.[22,33] The presence and formation of this SiO layer can be attributed to (1) post-HF treatment regrowth of native oxide on the Si surface before the Mo film deposition and (2) oxidation of the Si surface by oxygen from water molecules intercalated at the Si–Mo interface while heating up the samples during the sulfurization process. Unlike the work of Liu et al., we do not observe the formation of an interfacial silicon oxide at the surface of the MoS2 films.[36] ToF-SIMS measurements provide a depth profile of the chemical composition of the samples (Figure c). In addition to the expected elemental/molecular composition of the intended layers, we observed the presence of negatively charged chloride (Cl–) and hydroxyl (OH–) ions. The latter likely originate from the introduction of water during processing and consecutive catalytic water splitting. The methods section provides details on the ToF-SIMS measurements.

Figure 1

(a) Schematic diagram illustrating the fabrication process flow for metal–semiconductor–semiconductor (MSS) capacitors. (b) Schematic diagram showing the vapor-phase sulfurization growth process for the MoS2 films used as a dielectric in the MSS capacitors. (c) Top-view optical microscope image of the fabricated MSS capacitor.

Figure 2

(a) Raman spectrum of a vapor phase grown MoS2 film. (b) Cross-sectional transmission electron micrograph of an MSS structure indicating that the majority of the nanocrystalline MoS2 layers is aligned vertically. The formation of an SiO interfacial layer is also visible at the Si–MoS2 interface. (c) ToF-SIMS depth profile measurements confirming the presence of OH ions in the MSS structures. The SIMS profile further confirms the expected elemental composition of the MSS structure, that is, silicon, sulfur, MoS2, chromium, and gold. Profiles of identical species originating from each layer were added to obtain a good representation of the composition of the layers in the structure. To access the species of interest, the profiles were measured in the negative ion mode, which normally puts a negative loading on the species. (d) Schematic diagram illustrating the ToF-SIMS depth profile measurements, in which a heavier incident ion knocks out species from the target sample. Here the numbering 1–4 indicates the measurement sequence and the solid circles represent the species presented in the depth profile in panel c.

C–V and G–V measurements were carried out in a Lakeshore cryogenic probe station connected to a Keithley KI-590 admittance meter in vacuum (10–4 mbar) and at room temperature. C–V characteristics measured at 100 kHz signal frequency on the MoS2 capacitors with p- and n-Si substrates are shown in Figure . The shape of these graphs resembles that of typical metal/oxide/silicon (MOS) structures,[37] with capacitance saturation over a large voltage range for the p-type samples (Figure a). The n-type samples also exhibit saturation (Figure b), but leakage current dominates for gate voltages above 4 V. As a consequence, the measured capacitance starts to drop below the saturation level above that voltage (not shown). On the basis of the C–V measurements, we calculated the dielectric constant values for the vapor-phase grown MoS2 usingwhere the insulator capacitance Cins is analogous to the oxide capacitance of conventional MOS capacitors, CSiO is the IL capacitance, and CMoS is the MoS2 capacitance. In this calculation, Cins is considered to be the equivalent capacitance of the SiO and the MoS2 capacitors that are connected in series. It is obtained from the saturation part of the C–V curves shown in Figure . When the measured capacitance saturates, as observed in the C–V characteristics in the range from −4 to 0 V in Figure a and for about +4 V in Figure b, the total capacitance is given by the combination of the interfacial layer- and MoS2- capacitances (CSiOx and CMoS) which are independent of voltage (i.e., eq ).[37] The extracted dielectric constant values are in the range of 2.6–2.9. Santos and Kaxiras[38] suggested that the dielectric constant of MoS2 varies with applied external electric fields (Eext) and number of layers. In our measurements, the electric fields at which the capacitance started to saturate were in the range of 0.0033–0.02 V/Å. For this field range, the predicted MoS2 dielectric constant of approximately 3[38] is in reasonable agreement with the extracted values of the present work. However, we note that the theory was based on horizontally aligned MoS2 layers, while the experiments were carried out on MoS2 with vertically aligned layers (Figure b). Thus, the polycrystalline nature of the experimental MoS2 and its vertical layer orientation is likely to result in different measured dielectric constants compared to simulated data that assumes single crystal MoS2.

Figure 3

C–V measurements on MSS capacitors with (a) p-type Si and (b) n-type Si at 100 kHz AC signal frequency. Inset a: Schematic of the device structure with the wiring setup used during measurements. Schematics of band diagrams of the MSS capacitors with (c) p-type and (d) n-type Si, at thermal equilibrium.

The C–V measurements indicate that energy barriers exist between Si and MoS2 for both holes and electrons, and that they are sufficiently high to establish accumulation of carriers at the Si band edges (i.e., saturating CV curves). The magnitude of these barriers depends on energy band alignment, which could vary between the following two extremes: (1) Assuming that the band alignment is entirely determined by electron affinities, one would expect a “Type-I” (straddling) gap,[39] where the barrier heights are determined by the difference between the electron affinities of the two materials in contact. (2) Assuming that the alignment is mainly controlled by the existence of “virtual gap states”, a “Type-II” (staggered) gap[39] will form. In this case, the hole barrier is expected to be considerably larger than the electron barrier, which is in accordance with the present observation of current leakage mentioned earlier. In reality, however, one may expect a combination of the two phenomena.[40] The presence of two interfaces (i.e., Si/SiO and SiO/MoS2) in the present devices makes the situation even more complicated as the band alignment can be influenced by virtual gap states in both SiO and MoS2 layers. Furthermore, as will be discussed below, negative charge close to the Si/MoS2 interface may give rise to a bending of the MoS2 energy bands to form an additional barrier for electrons. On the basis of the saturation effects observed in the C–V data discussed above, we propose simplified energy band schemes (Figures c and 3d) for the present MSS structures. These band schemes feature a SiO transition layer, where x ≤ 2, between Si and MoS2. Compared to a standard pure SiO2 gate oxide, this interfacial layer seems to be more permeable to charge carriers. The leakage current through the SiO transition layer in the present MSS structures (Figure S1) was examined and found to be about 3 orders of magnitude higher than leakage current reported for standard SiO2 of comparable thickness and applied gate voltage.[41] This indicates that the interfacial layer in the current device is of poor quality, possibly due to oxygen deficiencies and other defects favoring leakage.

For further investigation, we performed bias-stress (BS) measurements on the MSS devices. BS measurements allow investigating charge dynamics in dielectrics and at their interfaces, and also to study the effect of interface states on the C–V and G–V characteristics. Here, a reference C–V curve was first measured without BS with 70 ms delay between data points. Next, bias stress of VGstress = 4 and −4 V was applied for 1 min, followed by C–V and G–V measurements that were run with the shortest possible delay between data points (i.e., 1 ms). This resulted in shifting of the curves along the voltage axis. Subsequent BS cycles were applied until the curves did not exhibit further observable shifts. Figure a shows C–V characteristics for the MSS capacitors on n-Si measured under positive BS of VGstress = 4 V, which shifts the curves to the left along the voltage axis. In addition, the curves exhibit a hump that increases for increasing positive BS cycles. A similar development can also be observed in the G–V plots presented in Figure b. Here, the growing maxima in the G–V curves is a clear indication for the existence of interface states.[42,43] A second maximum develops that quickly becomes larger in value than the initial maximum of the G–V curves. The horizontal shift and increase in the hump intensity of the C–V curves are consistent with the observed shift and increase in the peak intensity of the G–V curves. Negative BS measurements (with VGstress = −4 V) were conducted on the same device. This time, the C–V and G–V curves exhibit parallel shifts in the opposite direction as for positive BS, that is, to the right along the voltage axis (Figure c and 4d,). In contrast to positive BS, humps were not observed on the negative BS C–V curves and the maximum of the G–V peaks showed a gentle decreasing trend for increasing negative BS cycle number. In addition, the voltage shift was smaller than that for positive BS. Similar trends were observed in the C–V and G–V characteristics of samples with p-Si substrates under positive BS (Figure a and 5b), albeit with an additional “turnaround” effect after the first negative BS cycle, which will be discussed in detail later (Figure c and 5d). Similar trends were observed for both positive and negative BS C–V and G–V measurements carried out on other devices (see Figures S2 and S3).

Figure 4

Bias-stress (BS) C–V and G–V measurements on MSS capacitors with n-Si at 100 kHz AC signal frequency: (a) C–V characteristics showing clear shifts of the capacitance curves to the left under positive BS. (b) Corresponding G–V plots confirming the shifting trend. The voltages at which the conductance maxima occurs correspond to bias voltages assigned to distinct humps in the C–V curves. (c) C–V measurements under negative BS, where the capacitance curves shift to the right. (d) Corresponding G–V plots with a similar shift direction and with peaks of slightly decreasing amplitude. In all measurements, the first black curves were measured without BS and with a 70 ms delay between data points. Each of the remaining curves were measured successively after 1 min BS and with 1 ms delay. For clarity reasons, all the graphs in this figure present magnified versions of the measurements in a smaller voltage range. In addition, negative BS measurements were done first and positive BS next, but again for convenience during discussions, they are presented in the opposite order.

Figure 5

BS C–V and G–V measurements on MSS capacitors with p-Si at 100 kHz AC signal frequency: (a) C–V characteristics with clear shifts of the capacitance curves to the left under positive BS. (b) Corresponding G–V plots with peaks showing slight increase in amplitude and shifting to the left. (c) C–V measurements on the same device under negative BS. A “turn around” effect is observed: the first BS leads to a shift toward the left, but upon the second bias-stress cycle, the curves shift to the right. (d) Corresponding G–V plots with similar behavior. In all these measurements, the first black curves were measured without BS with a 70 ms delay between data points. The subsequent curves were measured after 1 min BS and with 1 ms delay. For clarity reasons, all the graphs in this figure present magnified versions of the measurements in a smaller voltage range. Negative BS measurements were done before those at positive BS, but for convenience they are presented in the opposite order.

The C–V data was further analyzed through simulations based on an equivalent circuit model.[43] This was inspired by the experimental evidence of negatively charged ions within MoS2 that may move in response to BS and interact with interface states to influence the capacitance measurements. The circuit configuration given by the capacitance meter to yield the measured quantities is depicted in Figure a. This configuration contains a capacitor and a conductor connected in parallel. However, the physical MSS system should be represented by more circuit elements (Figure b). This equivalent circuit model takes into account the capacitance contributions from the IL, CSiO, from MoS2, CMoS, and from the silicon depletion layer, Cs. The model also considers capacitance and conductance contributions from the interface states, Cit and Git, respectively. The capacitance and conductance contributions from interface states are initiated by the oscillation of the Si Fermi-level position (Δμ) with respect to the energy position (Δ) of the interface states with an energy distribution, Dit(ΔE). Depending on the energy position of the interface states with respect to the Fermi-level, charge carriers are captured and emitted by the states in pace with the angular frequency, ω, of the measurement AC signal. This periodic transfer of charge carriers from and into the interface states establishes the interface state capacitance, Cit, and conductance, Git, which influence the final measured quantities, Cm and Gm. In addition, since the Fermi-function is not a precise step function at finite temperatures, the capacitance meter cannot distinguish between capacitance contributions from charge carriers captured by traps with energy levels at the exact position of the Fermi-level and those within the tails of the Fermi function. To address this issue, it is appropriate to introduce a concept of capacitance density (χit), which represents the capacitance per unit area and unit energy.[37,43] The mathematical expression for this quantity can be formulated aswhere q is the electron charge, Dit is the energy distribution of interface states, e is the rate of emission of electrons at the trap, kB is Boltzmann’s constant, T is the absolute temperature, and f is the Fermi-function.

Figure 6

Calculation of C–V curves and fitting them to the experimental C–V data from MSS capacitors with n-Si measured under positive BS: (a) Equivalent circuit model with elements as measured by the C–V meter. (b) Equivalent circuit model with circuit elements representing the physical SSM device under test. (c) Calculated C–V curves (solid lines) fitted to the experimental C–V data measured at 100 kHz (dots). The first curve from the right represents data measured without BS and MC1, MC5 and MC13 are C–V curves measured after the 1st, 5th, and 13th BS cycle, respectively, as presented in Figure a. The abbreviation “MC” in the legend stands for “Measurement Cycle”. (d) Dit distributions assumed to fit the theoretical C–V curves to the experimental data. Good agreement between the simulated and measured C–V data in combination with the Dit trend strongly suggests that the negative C–V shift and the growing hump under positive BS is a result of the mobile negative ions in MoS2 moving away from the SiO–MoS2 interface, thereby reducing the electrostatic passivation of interface states.

Integrating the capacitance density along ΔE results in the interface state capacitance, Cit, for a given Fermi-level position (Δμ)The electron emission rates at the interface states are assumed to be much higher than the frequency of the AC probe signal from the capacitance meter, so that the trap states are completely emptied and filled within a period time of the AC signal. Therefore, the measured differential capacitance Cm can be calculated as[37,43]where Cm is the measured capacitance, CMoS is the MoS2 capacitance, CSiO is the IL (SiO) capacitance, CS stands for the silicon capacitance, and Cit is the interface state capacitance as calculated using eq .

The theoretical capacitance was calculated using eq and compared with experimental data. Figure c shows measured C–V curves (symbols) at four BS cycles and the corresponding theoretical fits (solid curves) by using Dit distributions shown in Figure d. Each Dit distribution was individually tuned to fit the respective theoretical C–V curve with the corresponding measured data. The model accurately describes the experimental data, including the amplitudes of the observed C–V humps (Figure c). These results confirm that the increasing amplitude of the C–V humps originate from the peaks in the Dit distribution of interface states. The model in combination with the good fit to the experimental data also suggests that the active interface states, Dit, changes in concentration and energy maximum as a function of positive BS cycles.

These horizontal and vertical shifts of the C–V and G–V curves in response to BS can be attributed to the movement of negative mobile charges inside the MoS2 bulk, and their interactions with interface electron states. Under negative BS, mobile negative charges are pushed toward the IL-MoS2 interface, leading to positive parallel shifts in the C–V and G–V curves as observed in Figure c and 4d. This situation is similar to the electric field induced movement of sodium ions in SiO2 studied in the early days of MOS development.[44] Furthermore, as the negative mobile charges approach the interface, Coulomb forces may disturb the electron potential of the states. This would in turn influence their energy positions and even give rise to a passivation effect similar to that caused by hydrogen in SiO2,[45] leading to the observed reduction of humps in the C–V curves (Figure c and 4d). On the other hand, positive BS drags mobile negative charges away from the IL–MoS2 interface, thus removing their influence on the interface states. This causes a decrease in the negative charge at the interface and an increase in concentration of active interface states that can capture and emit electrons. As a result, negative voltage shifts and pronounced humps are observed in the C–V curves in Figure a. The same effect also manifested in the negative voltage shifts and increasing peaks of the G–V curves (Figure b), which indicates increasing interface state concentration. Positive BS on the p-type samples (Figures a and 5b) resulted in responses similar to that for n-type samples. The shape of the interface state distributions resemble that of the Pb centers occurring at SiO/Si interfaces.[46,47] Their presence is attributed to the interfacial SiO layer formed on Si, which is very similar to the well-documented examples from research toward integration of high-k oxides in Si MOSFETs.[42,43]

Finally, the “turn-around” effect observed in the C–V and G–V curves for p-type samples after the first negative BS cycle warrants a discussion. Here, an initial shift of the curves in the negative voltage direction is followed by positive voltage shifts for succeeding stress cycles (Figure c and 5d). This indicates that either an increasing positive charge or a decreasing negative charge occurs close to the silicon side of the capacitor after the first cycle but not after those following. Taking into consideration the existence of hole accumulation at the Si/SiO interface during negative BS, conceivable origins of this effect could be the interaction of holes either with traps of the SiO layer or the moving ions, thus leaving a more positive oxide charge behind.

On the basis of the ToF-SIMS data, we propose that negatively charged mobile ions are responsible for the observed BS responses. In particular, because of a high possibility for adsorption of water molecules in the MoS2 layer during and after device fabrication, we consider hydroxyl ions (OH–) as probable candidates. These would be expected to originate from water splitting due to the catalytic properties of Cr and in particular MoS2.[48−52] The predominantly vertical orientation of the MoS2 layers may in particular facilitate the mobility along the van der Waals gaps, which are oriented parallel to the electric field.

The results show certain plasticity of the device behavior as ions move inside the MoS2 film. Polycrystalline MoS2 films may thus enable future devices for integrated circuits with synaptic plasticity, which is an indispensable feature for hardware-based neuromorphic computing.[8]

Conclusions

Capacitors with vapor phase-grown MoS2 layers as dielectric were fabricated and characterized in detail. TEM images revealed a nanocrystalline nature of MoS2 and the formation of an amorphous SiO interfacial layer between Si and MoS2. The extracted dielectric constants of MoS2 are in the range of 2.6–2.9 for electric fields ≤0.02 V/Å. In addition, ToF-SIMS depth profiles suggest the presence of OH– ions in the devices. From theoretical calculations that were fitted to the experimental data, Pb-like Dit peaks and their concentrations indicate the presence of significant amount of interface states and confirm the presence of mobile negative ions. Such features have so far been largely neglected in experiments using single- and multilayer MoS2 as an electronic material, for example, for few-layer MoS2 FETs. Since few layer 2D materials and their heterostructures are under intense investigation, this work should serve to alert the community about the downside of the catalytic behavior of MoS2, which may otherwise be explored in catalytic applications. Hence, this study indicates future challenges as the research on transition metal chalcogenides moves from exfoliated (near-perfect) flakes to materials grown with scalable, semiconductor fabrication compatible methods. Finally, ion- and defect-based[8] phenomena in 2D materials including MoS2 and graphene[53] may also be exploited in future neuromorphic computers, where neuroplasticity is a required feature.

Methods

Metal–semiconductor–semiconductor (MSS) capacitors in which MoS2 is sandwiched between a metal and Si were fabricated on p- and n-type silicon (Si) substrates. First, hydrofluoric acid (HF) was used to remove native silicon oxide from the Si surface, followed immediately by e-beam evaporation of ∼5 nm molybdenum (Mo) thin films on the Si substrates. Then, the samples were sulfurized in a tube furnace at 800 °C in argon (20 sccm) and sulfur atmosphere for a duration of 30 min.[54] Throughout the sulfurization process, sulfur was kept at an upstream location of the tube where the temperature was around 150 °C and the growth pressure was around 2 × 10–3 mbar. The growth process yielded ∼15 nm thick MoS2 films with height variations of approximately 1 nm, as confirmed by atomic force microscopy (AFM) measurements. Afterward, circular metal gates with a diameter of 100 μm were formed through a sequence of photolithography, deposition of a stack of chromium (Cr, 20 nm) and gold (Au, 120 nm) by thermal evaporation, followed by a lift-off process. Finally, the native oxide on the back side of the samples was removed by HF and a stack of Cr and Au was deposited as the back contact. A schematic diagram showing the complete process flow for fabricating the MSS capacitors is presented in Figure a. The vapor-phase sulfurization process is illustrated in Figure b and a top view optical microscope image of the as-fabricated device is shown in Figure c.

Raman spectroscopy and transmission electron microscopy (TEM) were carried out on the as synthesized MoS2 films to obtain information on the phase formation and structure of the films, respectively. A WITec alpha 300R system with 532 nm wavelength laser was used for the Raman measurements (Figure a), which were conducted using 1 mW of laser power and a 1800 g/mm grating. The TEM sample preparation was done in an FEI Helios NanoLab 400S FIB-SEM system, followed by NanoMill (cleaning with Ar ions) at 500 eV to get rid of the amorphous layer from the focused ion beam (FIB) irradiation. The clean samples (TEM lamellas) were then imaged using a FEI Tecnai G2 F20 TEM system at 200 kV. The resulting TEM image can be seen in Figure b. In addition, scanning electron microscopy (SEM) and X-ray diffraction (XRD) techniques were employed on the as-grown samples to obtain additional information. The resulting SEM image and XRD pattern confirm the homogeneous surface and 2H phase formation of MoS2, respectively (see Figure S4).

The chemical composition of the samples was also investigated with time-of-flight secondary ion mass spectrometry (ToF-SIMS) depth profiling. The ToF-SIMS measurements began by sputtering a target area on the samples with oxygen (O2) ions at 5 keV, which resulted in a 500 × 500 μm2 crater. This first step was carried out to remove possible contaminations on the topmost layers of the samples and reduce errors in the measurements. Then, bismuth ions (Bi+) were used at 25 keV to carry out the actual depth profile measurements within a smaller area (200 × 200 μm2) at the center of the larger crater. Each individual measurement was carried out after a 5 s presputtering step. Because the sample was sputtered with oxygen, metals form oxides, which appear in the mass spectra at relatively high signal abundance. The profiles presented in this work were measured in the negative ion mode, as the species of interest were best accessible that way. The ToF-SIMS depth profiles are presented in Figure c.

A Lakeshore cryogenic probe station connected to a Keithley KI-590 admittance meter was used to measure C–V and G–V on the as-fabricated MSS devices, in vacuum (10–4 mbar) and at room temperature. Bias stress measurements were carried out such that the devices were first stressed at V = ±4 V for 1 min and then followed by a quick C–V measurement. The experimental data were then compared to a model calculated using eq and Dit distributions as shown in Figure . Each Dit distribution was individually tuned so that the respective theoretical C–V curve fit the corresponding experimental data.