Locally Gated SnS2/hBN Thin Film Transistors with a Broadband Photoresponse.

Next-generation flexible and transparent electronics demand newer materials with superior characteristics. Tin dichalcogenides, Sn(S,Se)2, are layered crystal materials that show promise for implementation in flexible electronics and optoelectronics. They have band gap energies that are dependent on their atomic layer number and selenium content. A variety of studies has focused in particular on tin disulfide (SnS2) channel transistors with conventional silicon substrates. However, the effort of interchanging the gate dielectric by utilizing high-quality hexagonal boron nitride (hBN) still remains. In this work, the hBN coupled SnS2 thin film transistors are demonstrated with bottom-gated device configuration. The electrical transport characteristics of the SnS2 channel transistor present a high current on/off ratio, reaching as high as 105 and a ten-fold enhancement in subthreshold swing compared to a high-κ dielectric covered device. We also demonstrate the spectral photoresponsivity from ultraviolet to infrared in a multi-layered SnS2 phototransistor. The device architecture is suitable to promote diverse studied on flexible and transparent thin film transistors for further applications.

Introduction

An emerging new two-dimensional (2D) material is metal tin dichalcogenides, which have a layered structure composed of an earth-abundant compound solid. It is currently being considered as a promising candidate for flexible and heterostructured electronics[1-3]. Remarkably, the tin-based chalcogenide alloy SnS2−xSex shows a broad modification of the band gap with a selenium composition (for example, 2.07 eV and 0.97 eV for SnS2 and SnSe2, respectively)[4-6], which provides new possibilities for optoelectronics[7]. Only a few studies have investigated the mechanical characteristics of tin dichalcogenides so far. However, the covalently bonded SnS2−xSex alloy has shown that its lattice structure has a hexagonal CdI2-type, analogous to the widely investigated molybdenum disulfide (MoS2); this led us to expect that the alloy would have a higher strain limit than that of ionic-bonded bulk semiconductors[8]. Moreover, Mitzi et al. demonstrated that the soluble semiconducting SnS2−xSex can offer solution-processed thin films, making the integration of polymer substrate accessible[1]. All of these properties give this type of material great potential to meet the criteria for wearable and flexible devices[8].

Pan et al. investigated an SnS2−xSex crystal-based thin film transistor (TFT) under different x-contains, finding that the current on/off ratio was heavily decreased in the selenium-rich channel because of its large electron concentration[9]. This has motivated significant efforts to investigate the SnS2 crystal for field-effect transistors (FETs)[10,11] and photodetector applications[12-14]. For instance, an SnS2 nano-membrane FET with universal back-gated device geometry reported by De et al. exhibited a high switching ratio of up to 106 and a poor subthreshold swing (SS)[11]. Other works have confirmed this finding and further shown that the SS parameter was typically observed in dozens of volts per decade range. The device architecture in the form of a top-gated FET capped by a high-κ Al2O3 layer demonstrated similar subthreshold swing values approximately 10 V/decade[10]. It is believed that the trapped charges located between 2D and conventional oxide significantly influence the quality of the interface. Because layered solid crystals lack dangling bonds, the materials provide primary advantages in building heterostructures that combine diverse 2D layers into a three-dimension[15]. However, no study has yet reported research of transistors encapsulated by a wide band-gap 2D dielectric (5–7 eV)[16,17] that is a hexagonal boron nitride (hBN) with an integrated high-quality SnS2 nanosheet.

In this study, we construct a multi-layered SnS2 channel device incorporating hBN as a gate dielectric. Taking a different approach from other published works, the proposed transistors have a locally gated geometry instead of using universal silicon back-gating. We report a substantial improvement of the SS parameter of the device and characterize the effect of the Schottky-limited metal/semiconductor contact to describe the thermally activated transport. Furthermore, for the phototransistor, we also include the photoelectric behavior of the light-exposed SnS2. It appears that the SnS2 crystal responds to a wide range of photon spectra.

Results

Figure 1a schematically illustrates the device geometry of the proposed SnS2/hBN transistors, where atomically flat hBN acted as the gate dielectric[18] and a multi-layered SnS2 nanosheet was used as the carrier transport layer. Constructing the bottom encapsulation of hBN is beneficial because the SnS2 layer is far from the underlying potential fluctuation (SiO2 substrate). Our recent investigation showed that the interface trap sites located at the 2D/SiO2 interface could represent more than 1012 states/cm2eV[19]. Because contamination should be avoided during the fabrication process, we used a polymer-incorporated Scotch-tape residual-free technique to minimize the use of chemical solvents. In contrast to the wet transfer method described in other reports, this technique has the ability to control the interface trap state DIT down to the 1010 states/cm2eV range for a suspended 2D channel structure[19]. In this work, we fabricated more than five SnS2 devices with typical S/D dimensions: a channel length/width (L/W) ratio of 0.3 and a gate lead with a width of 5 μm. Optical images of the step-by-step preparation of the hetero-structured device are depicted in Fig. 1b. The as-made devices were subsequently characterized via atomic force microscope (AFM) analysis to quantify the thickness of the hBN dielectric and the SnS2, as illustrated in the left inset of Fig. 1c. The AFM cross-sectional profiles labeled line A (black) and line B (red) indicate a clear overlap between the channel area and the local gate, as illustrated in Fig. 1c. For the material characterization, the Raman spectra of the as-exfoliated SnS2 exhibit two non-degenerated scattering modes, with the out-of-plane A1g mode located at 320.6 cm−1 and the weak in-plane Eg peak located at 213.5 cm−1 (see the Supplementary, Fig. S1) under room temperature (see Fig. 2a, left). The data are in agreement with those of previous works[20,21]. On the other hand, in-plane mode, E2g of hBN is displayed in Fig. 2a right in consistent with other literature (The full Raman spectra of the heterojunction area can be seen in Fig. 2b)[22].

Figure 1

(a) 3D schematic representation of a bottom-gated SnS2/hBN heterostructure transistor. The high-quality hBN insulator proves to be an ultra-flat surface acting as a substrate for the precisely aligned SnS2 layer. (b) Optical images of the deposition of the hBN flake on the gold gate (left), the transfer of SnS2 (thickness typically in 1–30 nm range) onto the top of the hBN (middle), and the defined metal leads for source/drain contact (right). (c) The height profiles for lines A and B acquired from the AFM image (inset, left) of the device. The scale bar is 5 μm. Inset (right): 3D topography for the hBN on the SiO2, showing about a 30 nm thickness.

Figure 2

(a) Raman spectra of the multi-layered SnS2 (left panel) and the hBN (right panel). From the data, the Raman peaks for SnS2 and hBN occur respectively at 320.6 and 1372.4 cm−1. (b) Raman signal taken in the SnS2/hBN heterostructure region, showing peaks for the A1g mode of SnS2 and E2g mode of hBN. Insets: Raman frequency mapping image displaying the E2g peak intensity (left) and the A1g peak intensity (right), respectively, for hBN and SnS2. The scale bar is 5 μm.

Next, we proceed to examine the SnS2 channel TFTs and the influence of the hBN on the SS performance. Figure 3a shows the drain current IDS behavior of the devices as a function of the gate voltage VG under a constant drain voltage VDS of 0.7 V, exhibiting an SS of 585 mV/decade in a 30-nm-thick hBN inserted device. The different drain voltages also revealed similar subthreshold swing slope characteristics (see Supplementary, Fig. S2a). This value is one order of magnitude smaller than that of a high-κ (Al2O3) covered SnS2 transistor (in a top-gated configuration)[10]. It is well known that SS = ln(10)(kBT/e)(1 + η) and η = (CD + CIT)/CBN, where kB is the Boltzmann constant, T is the absolute temperature, e is the elemental charge, CD is the depletion capacitance, CIT = e2DIT is the interface trap capacitance, and CBN is the bottom-gate capacitance[19]. Thus, our devices demonstrated a factor η ≈ 8. Despite implications that high-quality SnS2/hBN contact is indicated, the research has not yet fully explained how the interfacial quality is correlated with the electronic characteristics, especially for a gate stack. Nonetheless, we attribute such SS enhancement to the highly coupled interface with negligible chemical residues. Hysteretic effect in IDS-VG characteristics often reflects the quality of channel/dielectric junction. The interfacial quality was further confirmed by the forward and backward direction sweeping of IDS − VG transfer curves which results a negligible hysteresis by amount of <200 mV as displayed in Fig. S2b. Consistent results were observed in all of the samples with current switching ratios in the 104 to 105 range and n-type conduction, as described in the literature[9,11,13]. The transconductance gM defined by dIDS/dVG displays a maximum value of ~0.12 μS at VDS = 0.7 V, as displayed in the inset of Fig. 3b. An important figure of merit of the transistor field-effect mobility μFE is determined by the relationship μFE = gM/CBNVDS × (L/W), where CBN = εBNε0/dBN (dBN = 30 nm is the thickness of the hBN layer and εBN = 3–4 is the dielectric constant of the hBN)[23]. As a result, μFE is calculated to be 0.1–0.5 cm2/Vs, comparable to those of single-layered MoS2 (0.1–10 cm2/Vs range)[24]. It should be note that different growth method commonly influences the electrical properties of SnS2 crystal. Song et al.[10], De et al.[11] and Ahn et al.[33] reported the mobility of approximately 1–2 cm2/Vs from SnS2 grown by vapor transport technique. However, the SnS2 solid crystal prepared by vertical Bridgman technique have showed poor mobility around 0.1 cm2/Vs[13]. Beside contact engineering and dielectric interface improvement, the material’s mobility seems influenced by growth method of SnS2.

Figure 3

(a) Semi-log (left axis, red) and linear (right axis, blue) scale IDS–VG transfer characteristics of the multi-layered SnS2 transistor biased at VDS = 0.7 V. The device exhibited an SS as low as 585 mV/decade and an on/off ratio of approximately 105 at room temperature. (b) IDS–VDS output curves for various applied gate bias values from −3 to 3 V. The region in the black circle shows the nonlinear property. Inset: transconductance versus bottom-gate voltage at VDS = 0.7 V, resulting in a maximum gM peak of 0.12 μS. (c) The extracted activation energy as a function of applied gate voltage. The Schottky barrier height is evaluated to be 135 meV for the Ni/SnS2 interface. Inset: I-V characteristics under small VDS bias.

To establish efficient carrier injection from outside (e.g., S/D metal), which is needed to enhance the device performance, the contact issues have been preliminarily investigated for the MoS2 system, and several novel approaches have been suggested[25]. So far, the ohmic contact formation for SnS2 materials is still unclear. Nevertheless, a linear increment in IDS can be observed for different VG bias conditions, suggesting an ohmic-like contact at the nickel/SnS2 junction at a small VDS bias range, as depicted in the inset of Fig. 3c. However, an ambiguous result emerges when the VDS is extended to a few voltages (quasi-linear region, before current saturation): a slightly nonlinear dependence of IDS is found (indicated by the black circle) in IDS–VDS output characteristics of the SnS2 device, as shown in Fig. 3b. We attribute this nonlinear behavior to the rise of the Schottky barrier height, eϕSB because a contact mismatch occurs between the high work function, WF of nickel metal (WF = 5.2 eV)[26] and the electron affinity, eχs of SnS2 (eχs = 5.0 eV)[27]. Owing to the similarity in crystal structure and chalcogenide compound compared with MoS2 layered material, similar consequences could be expected for other 2D systems. To better address this point, we measured the temperature-dependent I–V characteristics as temperature varied from 300 to 410 K (Supplementary Information, Fig. S3). Carrier transport across a metal–semiconductor barrier involves a quantum mechanical tunneling and a thermionic-emission process, so that the devices measured at high temperature regime allowed suppression of the tunneling current contribution[25]. At a high temperature regime, an expression similar to the Arrhenius equation and also known as thermally activated transport model can be derived as gDS = g0exp(−EA/kBT), where gDS = dIDS/dVDS is the conductance, and g0 is the fitting parameter[19,25]. The conductance gDS fitted with this equation is depicted in Fig. S3b (see Supplementary Information). The activation energy EA as a function of VG acquired from Fig. S3b is illustrated in Fig. 3c. In this plot, we can determine a 135 meV of eϕSB for Ni/SnS2 contact by evaluation of the starting point of deviation from the linear response by following Radisavljevic and Kis[28]. Such Schottky barrier determination is based on activation energy measurement. The details of the evaluation method of ϕSB can be found in other literatures[28,29] as well as our previous pulications[19,25]. A measured EA = 0.18 eV at zero VG generally indicates the position of the impurity donor level with respect to the conduction band of SnS2, and the activation energy is close to the value of 0.14 eV reported by Pan et al. and the value of 0.13 eV reported by De et al.[9,11].

Figure 4a shows the I–V transfer curves with (photon energy of 2.48 eV, green line) and without (dark state, black line) monochromatic light illumination at VDS = 0.1 V. The current under illumination IILL, defined as IILL = IPH + IDA (IPH and IDA are the photocurrent and dark current, respectively), exhibits a dramatic IDS increment of the SnS2 phototransistor in both the on and off states of the device, whereas the incident light with an intensity of 23.5 μW has about a 30-fold influence in the off-state and 2-fold in the on-state. With light illumination on different states of the device (on-and off-states), the devices exhibit different photocurrent response. Lowering the Schottky barrier (on-state), an additional photocurrent excited by photo-induced band-to-band transition contributes to the drain current. Raising the Schottky barrier (off-state) restricts the dark current, resulting in a more pronounced photocurrent extraction. Therefore, we carefully conclude that photo-excited carrier transport primarily dominates over the thermionic and tunneling current, which is in agreement with other publications[30,31]. We found that the effective transconductance g’ M of the SnS2 channel under light illumination showed clear increasement compared to the dark state, as depicted in the inset of Fig. 4a. The SnS2 phototransistor was further exposed to different monochromatic lights ranging in λ from 500 to 1000 nm, representing the series photo-induced I–V transfer properties at the on-state of the device with VDS = 0.1 V, as displayed in Fig. 4b. Electron-hole pair generation by optical means usually requires an incident photon energy close to the band gap of the multi-layered SnS2. Interestingly, the device weakly responds to light with a long λ (such as 600 nm, corresponding to 2.07 eV), implying an extrinsic type of the phototransistor with a defect-assisted energy level introduced. This effect can be explained by the defect-level involvement of the band gap of SnS2; the transition between the defect-level and the conduction/valence band edge can contribute to IPH[29]. Photoresponsivity, RPH is an important metric of the phototransistor and is estimated by IPH/PL, where PL is the optical power (see Fig. S4) and the broad spectral response is shown in Fig. 4c. In this photoresponsivity calculations, calibration of device’s active area is excluded. The device performance exhibits an RPH of 0.47–0.65 mA/W at the visible light range and is reduced to 0.33 mA/W at infrared due to the weak light absorption with an applied gating of 7 V. The measured RPH as function of VG is given in Fig. S4a. The responsivity of SnS2/hBN devices is lower than that of MoS2 based phototransistor (over 343 A/W)[30], but it is higher than that in a SnS2 nanosheet photodetector reported by Tao et al. (around 1.13 × 10−3 mA/W under 532 nm photon wavelength)[32] and vapor transport synthesized SnS2 crystal reported by Ahn et al. (within 0.1–1 mA/W range)[33]. Alternatively, optical characteristics of SnS2 could be highly improved by synthesis technique, such as chemical vapor deposition (CVD) for minimizing sulfur vacancy. Yang et al. reported that the SnS2 flake photodetectors prepared by CVD method archive significant improvement in photoresponsivity exceeding 1.19 A/W at 400 nm light[34]. Analogues to MoS2 crystal fabrication, different growth process may create different amount of sulfur vacancy in SnS2 which have great impact on photodetector application as discussed by Xie et al. (details see their publication)[35]. Therefore, we believe that extrinsic type of device with wide spectral response is probably due to sulfur vacancy induced deep states near bottom of conduction band.

Figure 4

(a) Semi-log IDS–VG transfer characteristics of the SnS2-based phototransistor for the dark state and for 500 nm wavelength illuminated curves at VDS = 0.1 V. Inset: the effective transconductance of the device as a function of gate voltage. Black and red curves are the device under dark condition and 500-nm-wavelength light exposure, respectively. (b) Linear scale of transfer curves for different wavelengths (ranging from 500 to 1000 nm) in the accumulation region. (c) Photoresponsivity and detectivity of the device as functions of wavelength at VDS = 0.1 V, showing a maximum RPH of 0.65 mA/W.

Another key parameter is the detectivity, D* which is the reciprocal of the noise equivalent power, given by D* = RPHA1/2/(2eIDA)1/2. Here, A is the device effective area. The calculated D* value showed a typical range of 1.4 × 106 to 5.1 × 106 Jones at VDS = 0.1 V and VG = 7 V. Furthermore, the external quantum efficiency, EQE is measure of the ratio of the number of carriers produced by the number of photons. The EQE can be converted from RPH by employing EQE = RPHhc/λe, here h and c are Plank constant and speed of light, respectively. We observed approximately 0.1% of EQE at visible light range.

Discussion

We fabricated SnS2/hBN heterostructured devices and characterized the devices by electrical and optical measurements techniques. The interfacial behavior between the SnS2 and hBN layered crystal is discussed. The locally placed gate separated by an hBN insulating layer presented an efficient modulation of the channel conductance with a current on/off ratio of up to ~105. The insertion of an ultra-flat dielectric layer allowed the device to exhibit SS values as low as 585 mV/decade. The detailed temperature-dependent electrical transport measurements led to the determination of eϕSB = 135 meV at the nickel/SnS2 interface. Moreover, we demonstrated the extrinsic type of the SnS2-based phototransistor with a wide range of light response and a high photoresponsivity of approximately 0.7 mA/W.

Methods

The bottom-gated SnS2 devices were fabricated on a thermally oxidized n+-type silicon substrate in which a 90-nm-thick SiO2 insulating layer offered electrical isolation from the back-gate, as well as optical detectability for the ultrathin nanosheet via optical contrast. The bottom electrode that served as both the optical indicator and the gate terminal of the transistor was pre-defined onto a silicon substrate by utilizing a standard photolithography process. We used SnS2 and hBN bulk solids obtained from the 2D semiconductor Inc. to generate nano-flakes using a Scotch-tape mechanical exfoliation method. We employed a technique developed in our previous work called “dry transfer,” based on a polydimethylsiloxane framework, to transfer the desired hBN flake onto the pre-patterned gold bottom-gate[2,19,25]. Subsequently, we deposited a piece of SnS2 on top of the hBN layer using the same technique. The SnS2 channel conductivity was monitored via metallization of the source/drain electrodes using a thermal evaporator system under a deposition rate of 5 Å/s to form a nickel/gold metal stack. An AFM (Park Systems, XE-100) operated under noncontact mode with a Nanosensor AR5-NCH tip was employed to characterize the topographic images of the devices. Raman signals were collected via commercially available confocal Raman spectroscopy (WiTec, alpha 300) with the excitation laser line of λ = 488 nm in ambient conditions.

The electrical transport properties of the SnS2/hBN devices were obtained with a semiconductor parameter analyzer (Hewlett Packard, 4156 A) in a vacuum cryostat (ASK, 700 K) under a pressure of 10−3 Torr. The photo-induced I–V measurements were conducted similarly under ambient conditions. To probe the photocurrent measurements, light wavelength λ spectra ranging from 300 to 1000 nm were generated by a system that consisted of a 300 W Xenon Arc lamp, a power supply (Newport, 69911), and an automated 1/8 m monochromator (Newport, 74004) with double grating. The excitation light intensity was recorded through a silicon photodiode detector (Newport, 918D-UV-OD3) mounted optical power meter (Newport, 1918-C). The collected power and irradiance data as function of photon wavelength is given in Fig. S4(b). During the photoresponse characterization, the device (active area, ~10−7 cm2) was illuminated by a monochromatic light guided by fused silica fiber optic bundle (Newport, 77577) with typical 3 mm in diameter uniform beam.