Deep-submicron Graphene Field-Effect Transistors with State-of-Art fmax.

In order to conquer the short-channel effects that limit conventional ultra-scale semiconductor devices, two-dimensional materials, as an option of ultimate thin channels, receive wide attention. Graphene, in particular, bears great expectations because of its supreme carrier mobility and saturation velocity. However, its main disadvantage, the lack of bandgap, has not been satisfactorily solved. As a result, maximum oscillation frequency (fmax) which indicates transistors' power amplification ability has been disappointing. Here, we present submicron field-effect transistors with specially designed low-resistance gate and excellent source/drain contact, and therefore significantly improved fmax. The fabrication was assisted by the advanced 8-inch CMOS back-end-of-line technology. A 200-nm-gate-length GFET achieves fT/fmax = 35.4/50 GHz. All GFET samples with gate lengths ranging from 200 nm to 400 nm possess fmax 31-41% higher than fT, closely resembling Si n-channel MOSFETs at comparable technology nodes. These results re-strengthen the promise of graphene field-effect transistors in next generation semiconductor electronics.

In order to conquer short channel effects, two-dimensional materials receive wide attention nowadays1. Graphene, in particular, bears great expectations because of its supreme carrier transport properties2. However, even though the cutoff frequency (f) of graphene field-effect transistors (GFETs) exceed Si transistors34, the maximum oscillation frequency (f), as the most relevant metric to circuit performance, seriously lags behind. Promising circuit applications are limited in passive circuits56789. Typical f values are one order of magnitude lower than f310111213. For instance, the 46-nm-gate-length GFET in Cheng et al.’s work delivered f/f of 212/8 GHz3. Wu et al. achieved f/f = 300/30 GHz and f/f = 120/44 GHz for GFETs with channel lengths of 40 nm and 120 nm, respectively10. The absence of bandgap is the primary drawback that limits f1. Introducing a bandgap by using bilayer or multilayer graphene is a straightforward idea. However, it suffers from synthesis difficulties1415. On the other hand, reduction of parasitic effects is a practical solution161718. Parasitic effects such as overlapping capacitance, contact resistance and gate resistance influence transistors’ RF performance. Several groups have already increased GFETs’ f by lowering the gate resistance16171819. Heer et al. achieved f up to 70 GHz for a 100 nm gate device, using mushroom T-shape top gates to lower the gate resistance16. Han et al. employed T-shape buried gates. Their work delivered f 25–43% higher than f, with the highest f of 20 GHz17.

In this work, the modern CMOS back-end-of-line (BEOL) technology has been employed to fabricate deep-submicron GFETs. GFETs with gate lengths ranging from 100 nm to 400 nm have been fabricated on 200 mm wafers by recently reported passive-first-active-last inverted process8920. In particular, buried gates with depth-to-width ratio up to six folds were achieved for the purpose of lowering the gate resistance. These GFETs achieve RF metrics (i.e. f and f) close to Si n-channel MOSFETs at comparable technology nodes. In particular, the 200-nm-gate-length GFET generates f/f = 50/35.4 GHz. The f/f ratio is also among the highest in literature.

Results and Disscussion

Fabrication

Schematic of the fabrication process flow is demonstrated in Fig. 1(a–h). 200 mm Si wafers with high resistivity (>1000 Ω cm) were used for the purpose of reducing substrate losses. 5 μm thick SiO2 layer was first deposited by PECVD method as the insulator layer. Metal structures were formed by Damascene process. For the purpose of increasing the depth-to-width ratio of the buried gates, 100 nm thick α-Si was deposited as the hard mark sacrifice layer. Definition of the deep-submicron gates was enabled by electron-beam lithography (EBL). Reactive ion etching (RIE) was used to realize the trenches. Owing to the large selection ratio between SiO2 and α-Si, the depth-to-width ratio was significant increased up to six, as illustrated in Fig. 1(b,c). After removal of α-Si, source/drain bottom contacts, interconnects and probing pads were defined by stepper lithography and etching. Bottom metals serve as an addition to top metals to ensure good contacts21. Then, tungsten was deposited by CVD method to fill in the trenches, followed by chemical-mechanical-planarization (CMP). Besides removing extra tungsten, it also guarantees the flatness of the wafer, necessary for the successfulness of the following graphene transfer process. HfO2 with equivalent oxide thickness (EOT) of 2 nm was deposited by atomic layer deposition (ALD) as the gate dielectric. The relative dielectric constant was about 20. The dielectric was defined by stepper lithography and removed by inductively coupled plasma (ICP) etching with BCl3 source.

Figure 1

Process flow.

(a) High-res Si substrate. (b) Definition of the gate on hard mask sacrificing layer. (c) Etching of the gate. (d) Definition and etching of the source/drain region bottom contacts. (e) W deposition and CMP. (f) Deposition of HfO2 gate dielectric. (g) Graphene transfer. (h) Patterning source/drain top contacts by lift-off process.

Figure 2(a) shows a photograph of a fabricated 200-mm wafer. Stand-alone submicron gate trenches with widths of 100 nm, 200 nm and 500 nm are displayed in Fig. 2(b). α-Si hard mask about 100 nm thick was indicated. Cross-section view of a 100-nm-gate-length GFET structure is demonstrated in the inset of Fig. 2(c), with the gate trench 100 nm long and 600 nm deep. Graphene in this work was formed by CVD method on Pt foils as previously reported2223. “Bubbling” method was used to transfer graphene to the patterned wafer on a die-by-die basis, limited by the maximum size of Pt foil2223. Graphene channels were patterned by contact mode contact lithography and oxygen plasma etching. All GFETs employed two-finger layout with each finger 6 μm wide. The source/drain contacts were defined by EBL, and went through 5 min ultraviolet-ozone (UVO) treatment before sputtering of 40 nm Pt and the following lift-off process. The ungated source/drain-gate spacer was about 200 nm. Stand-alone Hall device with size 36 μm × 8 μm resulted in carrier mobility about 3400 cm2v−1-s−1. Higher mobility is expected in fabricated GFETs, as smaller areas are less prone to defects. The probing pads feature 100 μm pitch in ground-signal-ground (GSG) layout. The GFETs have not gone through the passivation step for convenience. Various dielectrics passivation layers, such as Si3N424, BN25, Al2O326, etc., can be considered to further increase the stability and reliability of the graphene devices.

Figure 2

DC characterization.

(a) A fabricated 200 mm Si wafer. (b) Deep-submicron buried gate trenches etched with α-Si mask. Scale bar: 2 μm. (c) Cross-section view of a 100-nm-gate-length GFET structure. Scale bar: 2 μm. The inset shows the close-up view of the 100 nm buried gate. Scale bar: 1 μm. (d) TLM measurement of graphene-Pt contact resistance, which results in R = 550 Ω μm. The inset shows the SEM image of the TLM device. Scale bar: 10 μm. Transfer (e) and output (f) characteristics of the 100-nm-gate-length GFET. Transfer (g) and output (h) characteristics of a 300-nm-gate-length GFET. Cross-section views of the structures of a 200-nm-gate-length GFET (i) and a 300-nm-gate-length GFET (j).

Stand-alone transfer length measurement (TLM) patterns were fabricated along with the GFETs to measure the contact resistance, R. It indicates R of 550 Ω um as well as the sheet resistance of 880 Ω/sqr, as shown in Fig. 2(d) with the inset showing the SEM image of the TLM pattern. Typical metal contact resistance for CVD graphene ranges from few hundreds Ω to few kΩ27282930. R in this work is among the lowest, attributed to the high work function of Pt that induces more carriers underneath and UVO treatment that enhances the binding between metal and graphene3031. Other metal deposition recipes may also be considered as sputtering on graphene causes certain disorders. Figure 2(e) shows the transfer characteristics of the 100-nm-gate-length GFET with on-off ratio of roughly 2 folds. Figure 2(f) displays the output characteristics. It is worth noting that the two-point resistance R2pt is 1.4 kΩμm, indicating the contact resistance is less than 700 Ωμm, consistent with the stand-alone TML measurement. Top view of a fully processed 100-nm-gate-length GFET is shown in the inset of Fig. 2(f). Figure 2(f,g) present the transfer and output characteristics of a 300-nm-gate-length GFET, respectively. As expected, it demonstrates stronger gate modulation (i.e. transconductance) compared to the 100 nm counterpart. The two-point resistance R2pt also slightly increases to 1.5 kΩμm as the drain-to-source distance becomes longer. Figure 2(i,j) show the cross-section views of 200- and 300-nm-gate-length GFETs, respectively.

RF Performance and Discussion

High-frequency S-parameters of the GFETs were measured up to 40 GHz under ambient atmosphere using Agilent N8230C network analyzer. The system was calibrated with short-open-load-through (SOLT) method. Three-step de-embedding procedure was used32, which employed “open”, “through” and “short” structures to de-embed on-wafer parasitic components. (See Supporting Information) h21 and MUG of a 400-nm-gate-length GFET are displayed in Fig. 3(a,b). It delivers f/f of 18.6/28.4 GHz before de-embedding, and f/f of 25.5/35.5 GHz after de-embedding. As a reference, a recently reported 450-nm-gate-length GFET delivered f/f of 11.5/15 GHz17. Five successive GFETs with 400 nm gate length are shown in Fig. 3(c), which indicate excellent performance uniformity. A small-signal model is built which enables the analysis on the role of each parameter. The schematic of the small-signal equivalent circuit is presented in Fig. 3(d). Different from that of a conventional transistor, r lies in the outer equivalent position on neither of gate-source (C) and gate-drain (C) capacitance branches. It is because GFETs could not effectively pinch off and their behavior resembles linear-region conventional transistors. Fitting of the 400-nm-gate-length GFET with the small-signal model is demonstrated in Fig. 3(b), which delivers a close f/f of 25.2/32.3 GHz. Values for each component of the small-signal model are displayed in Table 1. The raw values extracted from the measured S-parameters are shown in Supporting Information. They are relatively stable in the measurement frequency range, confirming the effectiveness of the small-signal model.

Figure 3

RF characterization.

(a) h21 and MUG of a 400-nm-gate-length GFET before de-embedding. (b) h21 and MUG of the 400-nm-gate-length GFET after de-embedding and small-signal model fitting. (c) f/f of five 400-nm-gate-length GFETs across an array. (d) Equivalent circuit of the small-signal model. (e) f’s depedence on gate resistance, r.

Table 1

Values of the small-signal model parameters.

rg (Ω)	Cgs (fF)	Cgd (fF)	rds (Ω)	gm (mS)	τ
15	17.5	26	117	5.6	3.12

To verify r’s role in f, we varied r in a range including 5 Ω, 15 Ω, 30 Ω, 50 Ω, 100 Ω and 200 Ω, as depicted in Fig. 3(e). r = 15 Ω, marked red, generates the closest fitting as shown in Fig. 3(b). f increases or decreases with lower or higher r, respectively. f is inversely proportional to the square root of r, as indicated by the dashed guideline in Fig. 3(e), which is consistent with theoretical derivation as follows. (Derivation in detail is shown in Method section).

Unmodified gate is the primary reason why ordinary GFETs usually generate f one to two orders of magnitude lower than f 310111213. Unlike f, f is independent of r. It is worth mentioning that R and R have already been included in the transconductance term, g, of the small-signal model. Larger contact resistance leads to smaller g, thus f and f. The influence of R and R on g can be addressed by physics-based large-signal compact models33.

The h21 and MUG of a de-embedded 300-nm-gate-length GFET biased at Vds = 1.2 V is shown in Fig. 4(a). It achieves f/f = 34.2/45 GHz. Before de-embedding, f and f are 21.6 and 40 GHz, respectively (Supporting Information). The h21 and MUG of a de-embedded 200-nm-gate-length GFET biased at Vds = 1.0 V is shown in Fig. 4(b). f/f equal 35.4/50 GHz. Prior to de-embedding, f and f are 21.3 and 42 GHz, respectively (Supporting Information). The dash guide lines in these figures are in ideal −20 dB/dec slope for extrapolating f34. The f values of the 200-, 300- and 400-nm-gate-length GFETs outperform previous works with comparable gate lengths to the best of our knowledge. As parasite effect plays a larger role with shorter gate length, the 100-nm-gate-length GFET is retained for more careful characterization in following works. f’s dependence on gate length is shown in Supporting Information, revealing a relationship near to 1/L. Limited discrepancy may result from source/drain contact resistances, which play an unignorable role in GFETs33.

Figure 4

RF performance of the de-embeded 300- and 200-nm-gate-length GFETs.

h21 and MUG of a 300-nm-gate-length GFET (a) and a 200-nm-gate-length GFET (b).

A comparison with recently published GFETs and Si n-channel MOSFETs (NMOSs) with similar gate lengths is shown in Fig. 5. f/f of the GFETs is close to that of typical NMOSs at 0.25 μm and 0.35 μm technology nodes. And the f/f ratio largely exceeds previous GFET works.

Figure 5

Comparing f and f of published GFETs, Si n-channel MOSFETs and GFETs in this work.

Solid blue squares: Si n-channel MOSFETs at 0.25 μm3536 and 0.35 μm36 technology nodes. Solid red triangles: GFETs in this work. Hollow triangles: published submicron GFETs31012161837.

In summary, the advanced CMOS BEOL process has been employed in deep-submicron GFET fabrication. Thanks to the well-designed buried gate structure and lowered contact resistance, f has been increased significantly higher than before, rivaling Si transistor at comparable technology nodes. Considering its 8-inch wafer standard-process fabrication, GFETs are nearer to mass-production than ever. With the inverted process flow, one can also envision that future graphene RF components could be realized on CMOS backbones.

Methods

Graphene Synthesis and Transfer

Large scale monolayer graphene films were grown on 180 μm thick Pt foils (99.9 wt % metal basis, 10 mm × 10 mm) under ambient-pressure chemical vapor deposition (APCVD) method. The temperature was 1000 °C and CH4/H2 flow rate was set as 4.5/500 sccm. After growth, Pt foils are quickly pulled out of the high temperature area. PMMA photoresist was spun on graphene/Pt foil as the scaffold. Electrochemical delamination in NaOH solution was used to peel the graphene/PMMA off and transfer to pre-patterned dies. Raman spectrum of the monolayer graphene is shown in Supporting Information, Fig. S1.

Derivation of f -r relationship

The equivalent circuit of the small-signal model is shown in Fig. 6. Firstly, the input impedance, Z, and output impedance, Z, are calculated:

Figure 6

The input and output ports have to be conjugate-matched for maximum power transfer. Therefore, we have R = Z and R = Z. Then, MUG can be expressed as

When MUG = 1,

Additional Information

How to cite this article: Lyu, H. et al. Deep-submicron Graphene Field-Effect Transistors with State-of-Art fmax. Sci. Rep. 6, 35717; doi: 10.1038/srep35717 (2016).