| Literature DB >> 25104385 |
Paul A Merolla1, John V Arthur1, Rodrigo Alvarez-Icaza1, Andrew S Cassidy1, Jun Sawada2, Filipp Akopyan1, Bryan L Jackson1, Nabil Imam3, Chen Guo4, Yutaka Nakamura5, Bernard Brezzo6, Ivan Vo2, Steven K Esser1, Rathinakumar Appuswamy1, Brian Taba1, Arnon Amir1, Myron D Flickner1, William P Risk1, Rajit Manohar7, Dharmendra S Modha8.
Abstract
Inspired by the brain's structure, we have developed an efficient, scalable, and flexible non-von Neumann architecture that leverages contemporary silicon technology. To demonstrate, we built a 5.4-billion-transistor chip with 4096 neurosynaptic cores interconnected via an intrachip network that integrates 1 million programmable spiking neurons and 256 million configurable synapses. Chips can be tiled in two dimensions via an interchip communication interface, seamlessly scaling the architecture to a cortexlike sheet of arbitrary size. The architecture is well suited to many applications that use complex neural networks in real time, for example, multiobject detection and classification. With 400-pixel-by-240-pixel video input at 30 frames per second, the chip consumes 63 milliwatts.Entities:
Mesh:
Year: 2014 PMID: 25104385 DOI: 10.1126/science.1254642
Source DB: PubMed Journal: Science ISSN: 0036-8075 Impact factor: 47.728