| Literature DB >> 36133562 |
Jules Courtin1,2, Sylvain Le Gall3, Pascal Chrétien3, Alain Moréac1,2, Gabriel Delhaye1,2, Bruno Lépine1,2, Sylvain Tricot1,2, Pascal Turban1,2, Philippe Schieffer1,2, Jean-Christophe Le Breton1,2.
Abstract
The interface resistance at metal/semiconductor junctions has been a key issue for decades. The control of this resistance is dependent on the possibility to tune the Schottky barrier height. However, Fermi level pinning in these systems forbids a total control over interface resistance. The introduction of 2D crystals between semiconductor surfaces and metals may be an interesting route towards this goal. In this work, we study the influence of the introduction of a graphene monolayer between a metal and silicon on the Schottky barrier height. We used X-ray photoemission spectroscopy to rule out the presence of oxides at the interface, the absence of pinning of the Fermi level and the strong reduction of the Schottky barrier height. We then performed a multiscale transport analysis to determine the transport mechanism. The consistency in the measured barrier height at different scales confirms the good quality of our junctions and the role of graphene in the drastic reduction of the barrier height. This journal is © The Royal Society of Chemistry.Entities:
Year: 2019 PMID: 36133562 PMCID: PMC9418477 DOI: 10.1039/c9na00393b
Source DB: PubMed Journal: Nanoscale Adv ISSN: 2516-0230
Fig. 1(a) C 1s core level spectra of G/Si:H before and after 3 nm Au deposition. The C 1s level of HOPG is also shown. (b) Si 2p core level spectra of Si:H and G/Si:H before and after 3 nm Au deposition.
Fig. 2Schottky barrier height of Si and energy difference between the Dirac point and the Fermi level in the graphene layer as a function of Au coverage.
Fig. 3(a) 1/C2vs. V plot at 1 MHz for a Au/G/Si:H junction between 250 K and 330 K. (b) Schottky barrier height deduced from the capacitance–voltage measurements as a function of temperature.
Fig. 4(a) Current–voltage measurements between 220 K and 320 K for Au/G/Si:H. The room temperature I–V characteristic of a Au/Si contact is also shown. (b) Richardson plot of the Au/G/Si:H junction and (c) determination of the standard deviation from the mean barrier height.
Fig. 5(a) AFM close-up showing the four regions, (b) ResiScope mapping at the interface between uncovered and G covered Si under 30 nm Au, and (c) resistance distribution in the Au/G/Si area.