Direct constraint control for EM-based miniaturization of microwave passives.

Handling constraints imposed on physical dimensions of microwave circuits has become an important design consideration over the recent years. It is primarily fostered by the needs of emerging application areas such as 5G mobile communications, internet of things, or wearable/implantable devices. The size of conventional passive components is determined by the guided wavelength, and its reduction requires topological modifications, e.g., transmission line folding, or utilization of compact cells capitalizing on the slow-wave phenomenon. The resulting miniaturized structures are geometrically complex and typically exhibit strong cross coupling effects, which cannot be adequately accounted for by analytical or equivalent network models. Consequently, electromagnetic (EM)-driven parameter tuning is necessary, which is computationally expensive. When the primary objective is size reduction, the optimization task becomes far more challenging due to the presence of constraints related to electrical performance figures (bandwidth, power split ratio, etc.), which are all costly to evaluate. A popular solution approach is to utilize penalty functions. Therein, possible violations of constraints degrade the primary objective, thereby enforcing their satisfaction. Yet, the appropriate setup of penalty coefficients is a non-trivial problem by itself, and is often associated to extra computational expenses. In this work, we propose an explicit approach to constraint handling, which is combined with the trust-region gradient-search procedure. In our technique, the decision about the adjustment of the search radius is determined based on the reliability of rendering the feasible region boundary by linear approximation models of the constraints. Comprehensive numerical experiments conducted using three miniaturized coupler structures demonstrate superiority of the presented method over the penalty function paradigm. Apart from the efficacy, its appealing features include algorithmic simplicity, and no need for tailoring the procedure for a particular circuit to be optimized.

Introduction

One of the important considerations in the design of modern high-frequency circuits and systems is miniaturization. Small size has become a prerequisite for a growing number of application areas that include mobile communications[1], wearable[2] and implantable devices[3], internet of things[4], medical imaging[5], or energy harvesting[6]. Physical dimensions of conventional microwave passive components are related to the guided wavelength, which make them unsuitable for space-limited applications, except for structures implemented on high-permittivity substrates. In the context of circuit architecture, size reduction can be achieved by various means, including transmission line (TL) folding[7,8], replacement of conventional TLs by compact microstrip resonant cells (CMRCs)[9] capitalizing on slow-wave phenomenon[10], as well as the employment of various geometrical modifications (e.g., defected ground structures[11], slots[12], stubs[13], shorting pins[14], substrate integrated waveguides[15], etc.). The aforementioned techniques generally lead to complex, and often densely arranged layouts. The presence of electromagnetic (EM) cross-coupling effects within these structures makes the traditional characterization methods (analytical or equivalent network models) inadequate. Instead, reliable evaluation of miniaturized circuit has to rely on full-wave EM simulation tools.

Appropriate selection of the circuit architecture is only the first step of rendering a high-performance design. In order to achieve the smallest possible size while satisfying requirements imposed on the electrical parameters (allocation of operating frequencies, bandwidth, power split ratio, phase response), geometry parameters of the circuit have to be carefully tuned. Given multi-dimensional parameter spaces along with the necessity of handling several objectives and constraints, the parameter adjustment process needs to resort to rigorous numerical optimization algorithms[16,17]. At the same time, EM-driven optimization is computationally expensive: even local (e.g., gradient-based[18] or derivative-free[19]) procedures may require many dozens of EM analyses, whereas tasks such as global search[20], multi-objective design[21], or uncertainty quantification[22], are far costlier. Not surprisingly, the literature is replete with acceleration methods[23-27]. These include utilization of adjoint sensitivities[28] or sparse Jacobian updates[29] to expedite gradient-based procedures, the employment of dedicated solvers[30], and, more and more popular, surrogate-based procedures[31]. The latter may employ data-driven (or approximation-based)[32,33], and physics-based metamodels[34], but also machine learning frameworks[35]. The latter are often combined with sequential sampling methodologies[36] for iterative construction and refinement of the models. Some of popular approximation-based modelling methods in the context of EM-driven optimization include kriging[37], Gaussian process regression[38], neural networks in many variations (e.g.,[39-41]), support vector machines[42], polynomial chaos expansion[43]. Physics-based metamodels are most often constructed using space mapping[44], and response correction methods (e.g., adaptive response scaling[45], manifold mapping[46], etc.).

When it comes to EM-driven size reduction, a potentially high-cost of the process is only one of the challenges. The major issue is to control the constraints. As circuit miniaturization is generally detrimental to electrical performance figures, any practical design has to be a trade-off between achieving a possibly compact size and fulfilment of specifications imposed on the circuit characteristics. The latter are often expressed in terms of acceptance levels for return loss, bandwidth, power split, etc., over the frequency bands of interest. In mathematical terms, these conditions are essentially constraints. Their evaluation is computationally-heavy due to the involvement of EM analysis. Consequently, straightforward constraint handling is inconvenient. A widely used alternative is to incorporate penalty functions[47], in which the main objective (size reduction) is supplemented with a linear combination of appropriately quantified constraint violations[48]. The advantage of this approach is problem reformulation, so that it becomes a formally unconstrained endeavor. Yet, the efficacy of optimization dependent on the setup of the proportionality factors of the aforementioned linear combination (referred to as penalty coefficients). Tailoring their values to a specific structure is non-trivial and typically requires execution of test runs, contributing to the overall computational cost of the process.

This paper discusses a novel methodology for simulation-driven miniaturization of microwave passive components. Our approach employs explicit handling of design constraints, which are approximated—in any given iteration of the optimization process—by their linear approximation models. The quality of this approximation, in particular the predictions concerning solution feasibility, are verified upon generating a new solution, and used to govern the decision-making process that controls the search radius within the trust-region procedure being the main optimization algorithm. The decision-making factors include the feasibility status of the current design, as well as the amount of constraint violation improvement (of the lack thereof). Furthermore, the tolerance levels for constraint violations are gradually tightened in the course of the optimization process, governed by its convergence indicators. The proposed constraint handling method is simple to implement and does not require any setup of control parameters (as opposed to penalty coefficients within the penalty function approach). It is validated using three structures of miniaturized rat-race and branch-line couplers with the constraints imposed on the circuit bandwidth and power split ratio. The obtained results are benchmarked against the penalty function techniques. We demonstrate that the presented procedure allows for a precise control over constraints, as well as for achieving competitive miniaturization rates. Perhaps its most appealing feature is that it does not have to be tuned to any specific circuit at hand.

Miniaturization of microwave passives with direct constraint control

Here, we introduce the procedure for miniaturization of microwave components proposed in this work. “Simulation-based size reduction: problem formulation” provides the formulation of the miniaturization task. In “Explicit constraint handling: the concept”, we discuss the concept of direct control of CPU-heavy constraints within trust-region gradient-based algorithm. The technical details of controlling the tolerance levels for constraint violation as well as decision-making process that adjusts search radius are elaborated on in “Explicit constraint handling: constraint-related gain ratios”. Finally, “Explicit constraint handling: optimization algorithm” summarizes the entire procedure.

Simulation-based size reduction: problem formulation

We denote by  = [x1 ⋯ x] a vector of adjustable parameters of the circuit under design. For passive components, these are normally geometry parameters (circuit dimensions). Let A() be the circuit size, e.g., its footprint area. The objective is to reduce the size as much as possible, i.e., to solvewhere * is the optimum parameter vector to be identified, whereas U() is the objective function. In the case of miniaturization, we have U() = A(). The problem (Eq. 1) is subject to constraint, which can be ofor equality type

In this work, we will only consider inequality constraints, which are the most common. Also, an equality constraint η() = 0 can be represented in an inequality form as |η()|≤ 0.

Let us consider an example of a microwave coupler, which is to be miniaturized while satisfying the following conditions.

The power split ratio |S31(,f) − S21(,f)| is zero at f = f0 (the operating frequency);

The matching and isolation characteristics are supposed to satisfy |S11(,f)| ≤ − 20 dB, and |S41(,f)| ≤ − 20 dB for f ∈ F, where F is a frequency range of interest (intended circuit bandwidth).

These conditions can be formulated as constraints γ1() ≤ 0 and γ2() ≤ 0, with γ1() =||S31(,f) − S21(,f)||, and γ2() = max{f ∈ F: max{|S11(,f)|, |S41(,f)|}} + 20.

Thus, for the exemplary coupler, we may formulate the miniaturization task assubject to constraints

For the sake of illustration, let us consider another example of an optimization task, which is but oriented towards improving selected electrical performance figures rather than size reduction. Assume that the goal is to minimize the maximum reflection within the frequency range of interest of an impedance matching transformer. In this case, the merit function is defined as

In Eq. (7), |S11(,f)| stands for the circuit reflection, whereas F refers to the frequency range of interest.

Explicit constraint handling: the concept

Evaluation of constraints imposed on electrical characteristics of microwave components is computationally expensive: their values are obtained by post-processing EM simulation data. This is troublesome from the point of view of numerical optimization procedures, as local methods typically require constraint gradients. Unless adjoint sensitivities are available[49], estimation of these requires finite differentiation, and the constraints may not be differentiable due to their very formulation as minimax functions (cf. “Simulation-based size reduction: problem formulation”). Also, EM simulation results may contain a certain level of numerical noise, being a result of adaptive meshing techniques, or specific termination criteria used by the EM solvers. As mentioned before, a common mitigation method is a penalty function approach[47], where the cost function is defined through aggregation of the main objective (size reduction) and contributions from constraint violations, appropriately scaled using weighting factors (penalty coefficients). Although conceptually attractive, optimum setup of the coefficient values is generally an intricate task, often associated with preparatory optimization runs.

This paper offers an alternative approach to constraint handling, which is an explicit method. It employs linear approximation models of the system response, therefore, a natural choice for the underlying optimization algorithm is the trust-region (TR) framework[50]. The standard TR procedure yields a series of approximate solutions (, i = 0, 1, …, that converge to *. The new vector ( is obtained by solvingwhere U( is a first-order Taylor model of the scalar merit function U. The solution to Eq. (8) is restricted to the vicinity of ( determined by the size parameter δ(. Additionally, we have inequality constraints of the form of Eq. (2); equality constraints are not considered for the sake of simplicity, cf. “Simulation-based size reduction: problem formulation”. The TR radius δ( is adaptively adjusted using the standard TR rules (e.g.[50]).

The problem (Eq. 8) is solved using Matlab’s fmincon algorithm, which implements the Sequential Quadratic Programming (SQP) procedure, one of the state-of-the-art procedures for constrained continuous optimization. The SQP procedure directly handles geometry constraints (here, the TR condition || − (|| ≤ δ(), whereas the constraints related to electrical performance figures are controlled using the explicit approach being the subject of this paper. The details are explained in the remaining part of this section.

If size reduction is of interest, the evaluation of the merit function incurs negligible costs: the structure size can be obtained directly from the system geometry parameters, i.e., the vector . On the other hand, maintaining solution feasibility becomes problematic due to expensive constraints. In this work, constraint control is achieved by the incorporation of linearized models γ of the constraints γ, k = 1, …, nγ, and adaptive adjustment of the trust-region size parameter δ(. The decision-making process governing the latter involves quantification of the reliability of γ in predicting the feasibility status in the course of the optimization process.

In the following, we will denote as () the vector of EM-simulated outputs (e.g., S-parameters) of the circuit of interest. A first-order Taylor model (() of the response (), established at the design (, is definedwhere the Jacobian matrix of the component response at the design ( is denoted as ((). In most cases, it is estimated by means of finite differentiation. For the purpose of subsequent considerations, we will explicitly indicate that the constraints are functions of the circuit characteristics, i.e., we have γ = γ(()). Then, the linear model γ is defined as

When solving the trust-region sub-problem (Eq. 2), the exact constraints γ(()) will be replaced by their linearized versions (Eq. 10). The accuracy of representing γ by γ depends on a particular location in the parameter space and on the trust-region size parameter δ(, which is because ||γ(()) − γ()|| is proportional to || − (||2 (for sufficiently small design relocations). Consequently, a proper updating procedure for δ( is essential. In particular, maintaining small values of the TR radius improves the alignment between γ() and γ(r()), whereas increasing it allows for increased-size steps in the design space while solving (Eq. 8). The adjustment of δ( should take into account the solution feasibility predictions according to γ(), but also the actual feasibility status (as verified by EM simulation). At the generic level, the adaptation scheme is arranged the same way as for conventional TR algorithms[50], i.e.,

In Eq. (11), the coefficients m and m are used for incrementing and decrementing the TR region size, respectively, whereas θ and θ represent appropriate threshold. In our approach, we employ their typical values, i.e., we have m = 2 and m = 3, as well as θ = 0.75 and θ = 0.25[50]. As mentioned earlier, these are the typical values used in the TR algorithms. According to classical theory (e.g.[50]), the specific values of coefficients are not critical for the algorithm operation.

However, the decision-making factor θ in Eq. (11) is the gain ratio pertinent to the constraints. It compares the actual alteration of constraint violations to those predicted by the linear model for subsequent iterations (specifically, the (i + 1)th versus the ith one). The modification coefficients as well as the thresholds in Eq. (11) mimic the conventional rules of the TR frameworks (cf.[51]).

In the case of multiple constraints, the coefficient ρ is generalized to account for the worst-case situation over the entire set g, k = 1, …, n. We have

Definition of the factors θ for each γ(), k = 1, …, n, is pivotal to the successful operation of the proposed optimization procedure. It will be discussed at length in the next section.

Explicit constraint handling: constraint-related gain ratios

This section elaborates on the definition and evaluation of the constraint-based gain ratios θ, utilized to control the trust region size as discussed in “Explicit constraint handling: the concept”. In the following, we will denote by Γ( the threshold for accepting the violation of γ() at the iteration i. The threshold is iteration dependent for the reasons explained at the end of the section. At this point, we will outline the rules for computing the ratios θ utilized in decision-making process that governs the search radius adjustments:

Rule 1: If γ((()) > Γ(, i.e., the constraint violation before executing the (i + 1)th iteration exceeds the acceptance threshold, then

Rule 2: If γ(() ≤ Γ(, i.e., the constraint violation is at the acceptable level, then

Rule 3: If θ < 0 (as computed using Eqs. (13) or (14)) but γ((()) ≤ Γ(, i.e., EM-evaluated constraint violation is acceptable, then the value of θ is overwritten to θ = 0.5.

The above rules serve for two purposes. On the one hand, one needs to impose penalty on insufficient prediction accuracy of γ if the constraint violation is large (Rule 1), or the feasibility condition has not been improved in the case of minor constraint infringement (Rule 2). On the other hand, the conditions (Eqs. 13 and 14) are employed to promote sufficient prediction of γ by γ (cf. Eq. (13)), or relocation of the design towards the feasible region (cf. Eq. (14)). The role of Rule 3 is to overwrite the previous ones if the EM-evaluated constraint violation γ((()) at the candidate design ( is within the acceptance threshold. Rule 3 has been introduced to prevent erratic operation for the designs residing in the vicinity of the feasible region boundary, in particular, near-zero constraint infringements (either positive or negative) in any given iteration. The graphical illustration of acceptable and insufficient evaluation of the constraint γ by the linearized model γ has been provided in Fig. 1.

Figure 1

Prediction of design constraints by means of linear approximation model γ of (Eq. 10). The top picture illustrates relocation of the design from ( to ( obtained by solving (Eq. 8). In this example, ( is assumed feasible, whereas ( is allocated at the boundary of the feasible region according to the approximation model γ. The bottom-left picture illustrates a case of satisfactory constraint prediction by γ, i.e., the design ( is feasible according to the EM simulation data. The bottom-right picture shows a case of poor prediction: the design ( is infeasible according to the true constraint value evaluated through EM analysis. The latter will result in a reduction of the search region size δ( in the next iteration (cf. Eqs. (13, 14)).

In the remaining part of this section we discuss the acceptance thresholds Γ(. At the early stages of the optimization process (far from convergence), it is advantageous to relax the acceptance thresholds for constraint violation in order to facilitate identification of small-size designs. However, when close to convergence, the thresholds should be tightened to ensure more precise control over constraints. In practice, this is realized by adjusting the threshold values based on the convergence status of the optimization process. Let Γ be a user-defined maximum violation level. Further, let ε be a small positive number determining the algorithm termination. In this work, the termination condition is formulated as ||( − (||< ε or δ( < ε. For a given iteration i, let us define the convergence indicator

Note that ψ( is large when the optimization process is launched, and it is reduced to unity upon convergence. We also have the threshold

As Γ( is proportional to ψ(, it is initially equal to Γ, and gradually diminished to αΓ upon convergence. Here, α is assumes small values greater than zero, e.g., 0.1 or 0.01. This value is not of key importance for the operation of the procedure.

Explicit constraint handling: optimization algorithm

Figure 2 shows the operating flowchart of the proposed size reduction procedure with explicit handling of design constraints. Apart from the termination threshold, the algorithm only contains the following control parameters: the threshold Γ (maximum tolerance for constraint violation), and the scaling coefficient α. These parameters are not critical for the algorithm performance. As a matter of fact, we will keep these values fixed for all verification case studies considered in “Demonstration examples”. The acceptance of the candidate design ( produced by solving (Eq. 8) is based on the standard TR rules, i.e., it is accepted if the decision-making factor θ is positive, and rejected otherwise. In the latter case, the iteration is repeated with a reduced search region. Note that θ > 0 if either the violation of the constraint has been reduced to a sufficient extent, or the design was relocated to the feasible region.

Figure 2

Flow diagram of the proposed size reduction algorithm with explicit constraint handling.

Demonstration examples

This section summarizes the results of numerical experiments conducted to validate and benchmark the proposed size reduction approach. Verification is based on three compact microstrip couplers, including a branch-line and two rat-race circuits. Our procedure is compared to optimization involving penalty function approach in several variations featuring different setups of penalty coefficients. The performance figures of interest include the obtained circuit size, as well as the accuracy of controlling the constraints, related to the circuit bandwidth and the power split ratio.

Verification circuits

The considered circuits have been shown in Fig. 3. Their computational models are implemented in CST Microwave Studio and evaluated using the time-domain solver. In all cases, the main objective is reduction of the circuit footprint area. There are two constraints imposed on the circuit S-parameters: γ1() =||S31(,f0) − S21(,f0)|| − 0.1 dB, and γ2() = max{f ∈ F: max{|S11(,f)|, |S41(,f)|}} + 20 dB, where f0 is the center frequency, and F is the intended circuit bandwidth. Two scenarios are considered with different choice of bandwidth for each circuit.

Figure 3

Passive microstrip components utilized for verification of the proposed optimization procedure: (a) compact branch-line coupler (Circuit I)[52], (b) rat-race coupler with folder transmission lines (Circuit II)[53], (c) rat-race coupler with defected microstrip structure (Circuit III)[54].

The first constraint enforces equal power split ratio within 0.1 dB tolerance, whereas the second ensures that the circuit impedance matching and port isolation are better or equal − 20 dB within the operating band. Table 1 provides essential data about all three structures.

Table 1

Benchmark microwave components.

	Case study
	Circuit I	Circuit II	Circuit III
Substrate	AD300 (εr = 2.97, h = 0.76 mm)	RO4003 (εr = 3.38, h = 0.762 mm)	FR4 (εr = 4.4, h = 1.55 mm)
Design parameters	x = [g l1r la lb w1 w2r w3r w4r wa wb]T	x = [l1 l2 l3 d w w1]T	x = [L1 br g hfr s lfr]T
Other parameters	L = 2dL + Ls, Ls = 4w1 + 4 g + s + la + lb, W = 2dL + Ws, Ws = 4w1 + 4 g + s + 2wa, l1 = lbl1r, w2 = waw2r, w3 = w3rwa, and w4 = w4rwa, wc = 1.9 mm	d1 = d + |w − w1|, d = 1.0, w0 = 1.7, and l0 = 15 mm	L2 = L1 − g − w0, a = (lf − 17s)/16, b = (hf − s)br, lf = L2 lfr, lv = L1 − 2g − 2w0, and hf = s + (w0 − s)hfr; dW = dL = 10 mm
Operating parameters (design scenario I)	f0 = 1.5 GHz F = [1.45 1.55] GHz	f0 = 1.0 GHz F = [0.9 1.1] GHz	f0 = 1.2 GHz F = [1.15 1.25] GHz
Operating parameters (design scenario II)	f0 = 1.5 GHz F = [1.47 1.53] GHz	f0 = 1.0 GHz F = [0.95 1.05] GHz	f0 = 1.2 GHz F = [1.18 1.22] GHz
Initial designa	x(0) = [0.45 0.69 6.25 10.32 0.96 0.39 0.14 0.57 4.62 0.60]T	x(0) = [5.27 13.33 21.51 0.96 0.89 0.90]T	x(0) = [31.79 0.67 2.12 0.80 0.49 0.33]T

aInitial design obtained by optimizing the circuit for best matching/isolation within the frequency range F, under equal-power-split constraint.

(ε = 2.97, h = 0.76 mm)

(ε = 3.38, h = 0.762 mm)

(ε = 4.4, h = 1.55 mm)

Experimental setup and results

The proposed optimization procedure has been applied to the circuits of Fig. 3. In each case, the initial design (the last row of Table 1) was obtained by optimizing the respective circuits to improve the matching and isolation within the operating bandwidth F, subject to equal power split constraint. This means, in particular, that the starting points are feasible from the point of view of both constraints γ1 and γ2 (cf. “Verification circuits”). The termination threshold is set to ε = 10−3, the acceptance threshold are chosen to be Γ1.max = 1 dB, Γ2.max = 0.3 dB, and α = 0.1.

The results are compared to the algorithm employing the penalty function approach. Therein, the objective function is defined aswhere the penalty functions c1 and c2 measure relative constraint violations, i.e., we have

The benchmark algorithm is run for all combinations of the penalty coefficients β1 ∈ {10, 100, 1000, 10,000}, β2 ∈ {10, 100, 1000, 10,000}. This is to illustrate the fact that optimum performance of the algorithm requires identification of the appropriate setup of the penalty terms, and sub-optimal setup leads to inferior constraint control or miniaturization rates.

The numerical results have been gathered in Tables 2, 3 and 4. These include the achieved footprint area of the respective circuits, as well as constraint violations at the final design. Figures 4, 5 and 6 show the circuit characteristics at the initial and the optimized designs for all circuits, along with the history of the circuit footprint area and violation of constraints during the optimization run.

Table 2

Optimization results for Circuit I.

Optimization approach		Performance parameters
		Design scenario I (F = [1.45 1.55] GHz)			Design scenario II (F = [1.47 1.53] GHz)
Method	Setup	Footprint area A (mm2)	Violation of constraint γ1 (dB)	Violation of constraint γ2 (dB)	Footprint area A (mm2)	Violation of constraint γ1 (dB)	Violation of constraint γ2 (dB)
Implicit constraint handling (penalty function approach)	β1 = 101, β2 = 101	241	0.03	6.8	264	0.07	3.5
	β1 = 101, β2 = 102	259	0.06	5.3	264	0.07	3.5
	β1 = 101, β2 = 103	301	− 0.01	1.9	272	0.02	2.1
	β1 = 101, β2 = 104	325	0.01	0.2	293	0.02	0.2
	β1 = 102, β2 = 101	247	− 0.05	6.6	264	0.07	3.5
	β1 = 102, β2 = 102	258	− 0.02	5.7	276	0.00	1.7
	β1 = 102, β2 = 103	318	0.01	1.0	292	− 0.01	0.5
	β1 = 102, β2 = 104	319	0.00	0.3	297	− 0.08	0.3
	β1 = 103, β2 = 101	247	− 0.04	7.1	333	− 0.00	0.5
	β1 = 103, β2 = 102	264	− 0.03	53	335	− 0.01	1.0
	β1 = 103, β2 = 103	318	− 0.01	1.3	322	− 0.02	− 1.1
	β1 = 103, β2 = 104	319	0.00	0.2	301	− 0.05	0.1
	β1 = 104, β2 = 101	242	0.00	6.9	323	− 0.00	0.5
	β1 = 104, β2 = 102	258	− 0.05	5.7	292	− 0.06	0.8
	β1 = 104, β2 = 103	310	− 0.03	1.4	325	− 0.00	0.0
	β1 = 104, β2 = 104	317	0.00	0.4	302	− 0.07	0.1
Explicit constraint handling (this work)		323	0.00	0.0	293	− 0.05	0.3

Table 3

Optimization results for Circuit II.

Optimization approach		Performance parameters
		Design scenario I (F = [0.9 1.1] GHz)			Design scenario II (F = [0.95 1.05] GHz)
Method	Setup	Footprint area A (mm2)	Violation of constraint γ1 (dB)	Violation of constraint γ2 (dB)	Footprint area A (mm2)	Violation of constraint γ1 (dB)	Violation of constraint γ2 (dB)
Implicit constraint handling (penalty function approach)	β1 = 101, β2 = 101	124	0.01	16.8	114	0.00	16.6
	β1 = 101, β2 = 102	104	0.02	17.0	90	0.00	17.6
	β1 = 101, β2 = 103	464	0.27	3.2	439	0.21	2.9
	β1 = 101, β2 = 104	508	0.17	− 0.1	364	− 0.09	0.2
	β1 = 102, β2 = 101	593	0.04	− 3.4	593	0.04	− 5.2
	β1 = 102, β2 = 102	593	0.04	− 3.4	593	0.04	− 5.2
	β1 = 102, β2 = 103	538	0.07	− 1.9	593	0.04	− 5.2
	β1 = 102, β2 = 104	593	0.04	− 3.4	593	0.04	− 5.2
	β1 = 103, β2 = 101	595	0.04	− 3.4	595	0.04	− 5.2
	β1 = 103, β2 = 102	595	0.04	− 3.4	595	0.04	− 5.2
	β1 = 103, β2 = 103	595	0.04	− 3.4	595	0.04	− 5.2
	β1 = 103, β2 = 104	595	0.04	− 3.4	595	0.04	− 5.2
	β1 = 104, β2 = 101	595	0.04	− 3.4	595	0.04	− 5.2
	β1 = 104, β2 = 102	595	0.04	− 3.4	595	0.04	− 5.2
	β1 = 104, β2 = 103	595	0.04	− 3.4	595	0.04	− 5.2
	β1 = 104, β2 = 104	595	0.04	− 3.4	595	0.04	− 5.2
Explicit constraint handling (this work)		510	0.00	0.1	363	− 0.03	0.4

Table 4

Optimization results for Circuit III.

Optimization approach		Performance parameters
		Design scenario I (F = [1.15 1.25] GHz)			Design scenario II (F = [1.18 1.22] GHz)
Method	Setup	Footprint area A (mm2)	Violation of constraint γ1 (dB)	Violation of constraint γ2 (dB)	Footprint area A (mm2)	Violation of constraint γ1 (dB)	Violation of constraint γ2 (dB)
Implicit constraint handling (penalty function approach)	Z`β1 = 101, β2 = 101	1067	0.17	0.7	1043	0.12	− 0.7
	β1 = 101, β2 = 102	681	0.01	10.4	679	0.00	9.4
	β1 = 101, β2 = 103	1063	− 0.03	0.1	1063	− 0.03	− 1.0
	β1 = 101, β2 = 104	1097	0.02	− 0.1	1097	0.02	− 1.2
	β1 = 102, β2 = 101	1120	0.04	0.6	1120	0.04	− 0.5
	β1 = 102, β2 = 102	1134	0.00	− 0.3	1134	0.00	− 1.7
	β1 = 102, β2 = 103	1133	0.00	0.1	1133	0.00	− 1.2
	β1 = 102, β2 = 104	1038	− 0.03	1.1	1038	− 0.03	0.0
	β1 = 103, β2 = 101	1165	− 0.05	− 0.3	1165	− 0.05	− 1.7
	β1 = 103, β2 = 102	1119	0.01	− 0.1	1119	0.01	− 1.3
	β1 = 103, β2 = 103	1152	− 0.06	− 0.3	1152	− 0.06	− 1.6
	β1 = 103, β2 = 104	1117	− 0.08	− 0.1	1047	− 0.08	− 1.7
	β1 = 104, β2 = 101	1218	0.00	− 0.0	1136	− 0.02	0.2
	β1 = 104, β2 = 102	1208	0.00	− 0.2	1132	0.01	− 2.1
	β1 = 104, β2 = 103	1152	0.00	− 0.5	1152	0.00	− 1.7
	β1 = 104, β2 = 104	1152	− 0.02	− 0.1	1134	0.00	− 2.2
Explicit constraint handling (this work)		1106	− 0.04	− 0.1	1045	0.01	− 0.1

Figure 4

Initial (gray) and optimized (black) S-parameters of Circuit I. The vertical and horizontal lines mark the target operating bandwidth and the acceptance level for the matching |S11| and isolation |S41| responses. Also shown is the evolution of the circuit size and constraint violations (in case of feasibility, violations shown as zero): (a) design scenario I (bandwidth 1.45–1.55 GHz), (b) design scenario II (bandwidth 1.47–1.53 GHz).

Figure 5

Initial (gray) and optimized (black) S-parameters of Circuit II. The vertical and horizontal lines mark the target operating bandwidth and the acceptance level for the matching |S11| and isolation |S41| responses. Also shown is the evolution of the circuit size and constraint violations (in case of feasibility, violations shown as zero): (a) design scenario I (bandwidth 0.9–1.1 GHz), (b) design scenario II (bandwidth 0.95–1.05 GHz).

Figure 6

Initial (gray) and optimized (black) S-parameters of Circuit III. The vertical and horizontal lines mark the target operating bandwidth and the acceptance level for the matching |S11| and isolation |S41| responses. Also shown is the evolution of the circuit size and constraint violations (in case of feasibility, violations shown as zero): (a) design scenario I (bandwidth 1.15–1.25 GHz), (b) design scenario II (bandwidth 1.18–1.22 GHz).

Discussion

The results presented in “Experimental setup and results” allow us to formulate a number of remarks concerning performance of the proposed optimization procedure with explicit handling of design constraints. Furthermore, our methodology can be conclusively compared with the benchmark methods employing the penalty function approach. The observations are as follows.

The proposed algorithm performs consistently for all considered verification circuits. In particular, it enables a satisfactory control of both design constraints. There is no violation for power split ratio constraint observed, whereas the maximum violation for the matching/isolation constraint is only 0.5 dB for Circuit II (design scenario II); however, it should be noted that the acceptance threshold is − 20 dB.

The performance of benchmark methods is highly dependent on the penalty coefficient setup. Among sixteen combination of parameters, only a few lead to satisfactory results in terms of both ensuring good miniaturization ratio and sufficiently precise constraint handling. For Circuit I we have about three of such ‘good’ setups, for Circuit II there is only one (per design scenario), whereas for Circuit III about three.

For the particular setups ensuring good performance of the benchmark procedure, the obtained circuit sizes are comparable to those obtained by the proposed algorithm (which, on the other hand, does not require any setup or tailoring to the task at hand).

In the case of Circuit II, for most combinations of penalty coefficients featuring β1 ≥ 102, the optimization process becomes stuck at the early stages of the optimization process, leaving large feasibility margin for the second constraint. This is due to the fact that a large value of the first penalty coefficient along with a small margin for the power split ratio constraint (only 0.1 dB), makes the problem numerically challenging. More specifically, the objective function becomes highly nonlinear near the feasible region boundary, which hinders exploration of that region and leads to a premature convergence of the process. A similar effect can be observed for Circuit III, although it is less pronounced.

The proposed algorithm turns out to be less prone to the aforementioned issues due to the adaptive adjustment of the acceptance thresholds governed by the convergence status of the algorithm (cf. Eqs. (15, 16)).

The average costs of rendering the optimal designs by the proposed approach equal: 110, 80 and 55 full-wave simulations, for Circuit I, II and III, respectively. Whereas in the case of the benchmark procedure the corresponding costs are: 115, 57 and 45 EM simulations. Therefore, the proposed procedure is around 20% more expensive in terms of the number of EM analyses necessary for the algorithm to converge. Yet, given that in our approach there is virtually no need for tailoring the algorithm to render a satisfactory design meeting the design specifications, this additional cost seems to be justifiable. This is because tuning the optimization procedure to ensure its satisfactory operation normally entails additional computational expenses (e.g., for adjusting penalty coefficients in the case of implicit methods). Furthermore, the primary purpose of the presented technique was to improve the precision of controlling design constraints, and miniaturization rate, both of which have been conclusively demonstrated.

Given a large combined number of circuits, design scenarios, as well as penalty coefficient setups involved in this verification study, the observations summarized above should be categorized as conclusive. Overall, the performance of the presented procedure can be considered competitive over the benchmark (implicit) methods, both with respect to the accuracy of constraint handling and achievable miniaturization rates. The important advantages of the proposed algorithm include easy implementation and no need for adjusting any control parameters. The latter normally incurs extra computational expenses and may require a certain level of experience pertinent to optimization methods.

Conclusion

The purpose of this work was to propose a novel procedure for simulation-based miniaturization of microwave passives. Our approach involves direct control of constraints imposed on electrical performance figures of the circuit under design. Linear approximation models of the constraint functions are employed to make predictions concerning solution feasibility. Appropriately quantified quality of these predictions is utilized in the decision-making process that controls the search region size within the trust region framework. Furthermore, the constraint violation tolerance thresholds are governed by the convergence indicators of the optimization process in order to foster more aggressive size reduction at the early stages of the optimization process. Comprehensive numerical verification involving three microstrip couplers and six design scenarios demonstrate superior performance of the proposed technique as compared to the benchmark methods employing a penalty function approach for implicit constraint handling. Its major advantages include competitive size reduction ratios, accuracy in controlling constraint violation levels, consistency of results obtained for a variety of problems, straightforward implementation, as well as no need for tailoring the procedure to handle a particular microwave structure. The last feature is particularly important in practical applications: tuning the optimization procedure to ensure satisfactory operation (e.g., setting up penalty coefficients for implicit methods) normally entails additional computational expenses and may require optimization-related knowhow lacking by many microwave engineers.