A 619-pixel machine vision enhancement chip based on two-dimensional semiconductors.

The rapid development of machine vision applications demands hardware that can sense and process visual information in a single monolithic unit to avoid redundant data transfer. Here, we design and demonstrate a monolithic vision enhancement chip with light-sensing, memory, digital-to-analog conversion, and processing functions by implementing a 619-pixel with 8582 transistors and physical dimensions of 10 mm by 10 mm based on a wafer-scale two-dimensional (2D) monolayer molybdenum disulfide (MoS2). The light-sensing function with analog MoS2 transistor circuits offers low noise and high photosensitivity. Furthermore, we adopt a MoS2 analog processing circuit to dynamically adjust the photocurrent of individual imaging sensor, which yields a high dynamic light-sensing range greater than 90 decibels. The vision chip allows the applications for contrast enhancement and noise reduction of image processing. This large-scale monolithic chip based on 2D semiconductors shows multiple functions with light sensing, memory, and processing for artificial machine vision applications, exhibiting the potentials of 2D semiconductors for future electronics.

INTRODUCTION

Artificial machine vision plays a vital role in a wide range of applications, such as automotive, surveillance, and medical imaging fields (, ). Artificial machine vision has been inspired by the high efficiency and cognitive capability of human vision systems. The process of converting the light reflected by objects to an image can be simply described as the stimulation of retinal neurons to produce an action potential transmitted to the visual cortex in the brain, which then generates coherent images. The multiple neuron layers in conjunction with the flexible modulation of neuron connection strengths facilitate proper human vision functionality even under highly dynamic conditions. This case becomes more obvious when the difference between the lightest and darkest objects in a scene is beyond the response range of retina neurons. Therefore, human vision is a highly nonlinear process assisted by an activation function in conjunction with a multilayer neural network matching the dynamic range of the incident light (–).

Artificial vision systems mainly consist of light-sensing and current-stimulation function modules. Existing artificial vision systems are typically based on Si complementary metal-oxide semiconductor (CMOS) technology, where the light-sensing functionality is realized by light-sensing circuits that usually include multiple diodes and transimpedance amplifiers (–). The current-stimulation functionality is implemented by a retinal prosthesis module (–). However, conventional vision systems require complicated and high-bandwidth interconnections between the light-sensing circuits and the current-stimulation modules. These features unnecessarily increase the complexity of artificial vision systems and redundant data transfer. Therefore, the continued development of machine vision applications requires hardware that can sense and process visual information in a single monolithic unit. In addition, developing these monolithic chips on flexible, lightweight, transparent, and biocompatible films is of tremendous value for future biomedical applications (–).

Two-dimensional (2D) semiconductor materials (, ), such as molybdenum disulfide (MoS2) and tungsten disulfide (WS2), provide extraordinary electronic and optoelectronic characteristics because of improved electrostatic control with their ultrathin body and unique band structures (–). Moreover, the light-sensing devices based on 2D semiconductor can act as atomic-thin channels without dangling surface bonds (–). They provide reduced shot and flicker noises by confining charge carriers to the atomically thin vertical dimension (, ). This is particularly beneficial versus conventional Si-based CMOS photodiodes whose signal-to-noise ratio is particularly degraded by these noise sources (, ). The atomic-thin nature of 2D semiconductor films can also facilitate the transfer of 2D monolithic chips to appropriate flexible substrates, thus expanding their application scenarios (–).

In this work, we demonstrate the artificial machine vision enhancement (MVE) applications by fabricating a 619-pixel monolithic chip with physical dimensions of 10 mm by 10 mm based on a wafer-scale 2D monolayer MoS2, simultaneously realizing light-sensing, memory, processing, and noise reduction functions. The light-sensing devices are based on MoS2 field-effect transistors (FETs) with highly transparent top gate (TG) electrodes. The threshold voltage (VTH) of the FETs is effectively modulated by the intensity of incident light. A MoS2 analog processing circuit is designed to realize dynamic photocurrent adjustment of individual imaging sensors to emulate the characteristics of human retina neurons. The fabrication process enables the transfer of the 2D monolithic chip to flexible, lightweight, and biocompatible substrates. These results demonstrate that the proposed monolithic MVE chip shows the potential for future artificial machine vision applications.

RESULTS

Figure 1A shows a 2D monolayer MoS2 grown on a 2-inch sapphire wafer by chemical vapor deposition (CVD) method. An optical microscopy image of the MoS2 FET design with a transparent TG electrode is presented in Fig. 1B, where it shows the labeled TG, source (S), and drain (D). A 3D schematic illustrating the overall design is presented in Fig. 1C, which includes a HfO2 dielectric layer between the S, D, and TG electrodes as well as a very thin Au layer approximately 5 nm in thickness to ensure the high transparency of the TG and realize light sensing. The device-processing step is more compatible with conventional Si CMOS technologies and more suitable for large-scale circuit integration than a previously reported gate-first fabrication process that requires extra transfer processing of the MoS2 film (–). We adopted a process flow to fabricate a wafer-scale circuit of 2D MoS2 FETs with transparent TG electrodes (Fig. 1D; for more details, see the Supplementary Materials).

Fig. 1.

Wafer-scale fabrication and MoS2 phototransistor design.

(A) An image of a 2-inch wafer before and after MoS2 growth. (B) Optical microscopy image of an individual MoS2 FET with a transparent TG. (C) 3D schematic of an individual MoS2 TG-FET. (D) Process flow applied to fabricate MoS2-flexible TG-FET arrays. PI, polyimide.

We then characterized the uniformity of the MoS2 film by Raman spectroscopy mapping. Figure 2A is an intensity map obtained by normalizing the highest intensity of the A1g peak (405 cm−1) on the whole 2-inch MoS2 wafer. The Raman spectra obtained from 225 different positions on the 2-inch wafer are shown in the inset of the figure. The transfer characteristics of individual MoS2 TG-FET phototransistors were probed at a drain-source voltage of VDS = 0.2 V. The drain current (ID) versus TG voltage (VTG) transfer characteristics in Fig. 2B are obtained for each of the individual MoS2 TG-FET in the inset of the figure. The threshold voltage (VTH) and the field-effect mobility (μ) of the MoS2 TG-FETs are uniform for all FETs, which suggests the homogeneity of the wafer-scale fabrication process. The values of μ and VTH measured for each transistor are plotted as histograms in Fig. 2 (C and D, respectively), along with the Gaussian distributions fitted to the respective histograms. The average μ and average VTH are 65.7 cm2 V−1 s−1 and 1.58 V, respectively. More electrical measurement results were also obtained for MoS2 TG-FETs with different width-to-length (W/L) ratios. These were then used to build a compact 62-level SPICE (simulation program with integrated circuit emphasis) model (see the Supplementary Materials), which, in turn, facilitated the use of HSPICE to optimize specific W/L ratios of the MoS2 TG-FETs and simulate all circuits in the following discussion along with their integration.

Fig. 2.

Uniformity characterization of the MoS2 wafer and optoelectronic characteristics of the MoS2 transistors.

(A) Raman spectroscopy intensity map of a MoS2 TG-FET array normalized by the highest intensity at the A1g peak (405 cm−1), where the inset presents normalized Raman spectra obtained from 225 different locations on the 2-inch wafer. (B) Drain current (ID) versus TG voltage (VTG) transfer characteristics of the individual MoS2 TG-FETs in an array at a drain-source voltage VDS = 0.2 V in linear (left axis) and logarithmic (right axis) coordinates. The inset shows an optical image of the MoS2 TG-FET array; histograms of the (C) field-effect mobilities (μ) and (D) threshold voltages (VTH) were observed for each transistor in (B) along with the corresponding Gaussian distribution fitting results. (E to G) ID-VTG transfer characteristics of individual MoS2 TG-FETs under 450-, 550-, and 650-nm illumination with different power densities ranging from 33 to 669 μW/cm2. The corresponding photocurrent (IPH) versus VTG transfer characteristics are presented in the insets. (H to J) Power density dependence values for the difference between the value of VTH without and with illumination (∆VTH), IPH, and responsivity R under different illumination wavelengths of 450, 550, and 650 nm at VDS = 0.2 V and VTG = 3 V. a.u., arbitrary units.

The thin TG allows light illuminations to influence the transfer curves of MoS2 FETs as well, which is critical to achieving MVE. Figure 2 (E to G) shows the optoelectronic characteristics of a typical MoS2 TG-FET obtained under light illumination with wavelengths of 450, 550, and 650 nm and different incident optical power densities (PIN), respectively. The corresponding photocurrent (IPH) versus VTG transfer characteristics are presented in the insets. The results indicate that the values of ID and IPH obtained at a given VTG increase substantially with increasing PIN and decreasing wavelength. In addition, the difference between the value of VTH obtained without and with illumination (∆VTH), IPH, and optical responsivity (R) is plotted as a function of PIN for the different wavelengths at VDS = 0.2 V and VTG = 3 V in Fig. 2 (H to J, respectively). Figure 2 (H and I) shows that the values of ∆VTH and IPH both increase monotonically with increasing PIN and decreasing wavelength. This VTH shift is mainly due to the photogating effect (, ). In particular, we note a distinctively high ∆VTH value near 0.8 V under an illumination wavelength of 450 nm at a relatively small optical power density of 669 μW cm−2. This feature indicates that light illumination can act as an extra tuning knob similar to the TG (for more details, see the Supplementary Materials).

The observed linear log-log relationship between IPH and PIN can be defined according to the equation IPH = CPINα [i.e., log(IPH) = log(C) + αlog(PIN)], where C is a fitting parameter and α is an exponential factor (, ). Here, an increasing value of α represents an increasing efficiency of photon-induced charge carrier generation (). The fitted results are given by the solid lines in Fig. 2I, where α values of 0.728, 0.702, and 0.693 were applied to the data obtained at 450, 550, and 650 nm, respectively. Exponent values in the range of 0 < α < 1 mainly represent conditions where photo-induced charge carries arise from trap states and are typically applied to photodetectors dominated by photogating effects (). The measured spectral sensitivity indicates that the fabricated MoS2 TG-FET arrays can capture color images by incorporating appropriate color filters. Last, the results in Fig. 2J indicate that R decreases with both increasing PIN and increasing illumination wavelength. A relatively high R value of ~103 A/W is obtained at a wavelength of 450 nm and PIN = 33 μW/cm2.

We can obtain a tunable photosensitive current source based on MoS2 FETs to realize MVE. A TG MoS2 phototransistor denoted as M1 is illustrated schematically in Fig. 3A along with incident illumination. Accordingly, the output current (ID1) of M1 can be modulated by both the electrical signal VTG1 and incident light illumination of power density PIN, as shown in Fig. 3B for an illumination wavelength of 650 nm. However, the control of ID1 via VTG1 is not the best solution because of the nonlinear transfer curve of the device (Fig. 2B). This can be potentially addressed by adopting the MoS2 current mirror structure illustrated in Fig. 3C, in which the value of VTG1 applied to M1 is controlled by the current mirror transistor M2 (for details, see the Supplementary Materials). This was further illustrated by the optical microscope image of the as-fabricated current mirror circuit. Figure 3D shows that this circuit provides linear control of the output current ID1 with respect to the input bias current (Ibias). However, we also note that the relationship between ID1 and VTG1 is highly nonlinear. Last, Fig. 3D demonstrates that the slope of ID1 versus Ibias can be tuned by adjusting the width/length (W/L) ratio of the M1 and M2 TG-FETs. Thus, such a current mirror circuit can be conveniently optimized on the basis of specific application requirements.

Fig. 3.

MoS2 imaging sensor circuit design and characterization.

(A) Circuit schematic of a single MoS2 phototransistor M1 with an output current (ID1) controlled by both the TG voltage (VTG1) and the incident optical illumination density (PIN). (B) 2D plot of the measured ID1 as a function of VTG1 and PIN at an illumination wavelength of 650 nm. (C) Schematic of a current mirror circuit with MoS2 current mirror transistor M2 along with an optical microscope image of an as-fabricated circuit. GND, ground.(D) Measured ID1 as a function of the bias mirror current (Ibias) and VTG1 for different M1 and M2 geometrical combinations. (E) Schematic of the circuit in (C) with an added MoS2 transistor M3 that acts as a variable resistor to control the drain current of M3 (ID3) serving as the output current of the imaging sensor circuit along with an optical microscope image of an as-fabricated circuit. (F) 2D plot of the measured ID3 as a function of VTG3 and Ibias.

In practical applications, Ibias is usually routed to all pixels in an imaging sensor as a universal control. However, as illustrated in Fig. 3E, the output current obtained from an individual imaging sensor in the array can be further controlled by adding the MoS2 TG-FET denoted as M3 in series with M1. The TG-FET acts as a variable resistor controlled by VTG3. Thus, the output current ID3 of the sensor device is independently controllable according to the value of VTG3 for a given Ibias (see the Supplementary Materials), as shown in Fig. 3F. These results demonstrate that the output current range of each imaging sensor device can be independently adjusted from 20 fA to 4.3 μA by setting various combinations of VTG3 and Ibias. We define the value of the dynamic range according to Eq. 1where Imax and Imin are the maximum and minimum of output current, respectively. Vmax and Vmin are the voltages corresponding to Imax and Imin, respectively.

Controlling the output current of individual imaging sensors was made more convenient by introducing the MoS2 memory module to store the value of VTG3, as illustrated in Fig. 4A. The memory module consists of a single MoS2 transistor denoted as M0 and a single capacitor C. The structure functions like a dynamic random-access memory (DRAM) module, where the ON/OFF state of M0 is controlled by the gate voltage Vg. This charges C according to the value of Vw when Vg = 3 V. The value of Vw is stored in C when Vg = −3 V. A typical memory operation for the actual memory circuit is presented in Fig. 4B. Here, an initially positive Vg turns on M0, and C is charged according to the magnitude of Vw, while a negative Vg turns M0 off, and Vw is stored in C. We note that the ultralow leakage current (several fA) of the MoS2 channel in the OFF state enables the voltage stored on C to be maintained for more than 100 s with a voltage loss of less than 25%. This is substantially better than what can be maintained using a standard Si-based DRAM module.

Fig. 4.

MoS2 memory module and integrated imaging sensor designs.

(A) Memory module circuit consisting of transistor M0 and capacitor C along with an optical microscopy image of an as-fabricated circuit where the ON/OFF state of M0 is controlled by a gate voltage (Vg). (B) Typical memory operation for the actual memory circuit presented in (A). (C) Individual integrated image sensing unit with memory and analog signal processing modules along with an optical microscope image of an as-fabricated unit that includes a DAC to precisely control VTG3. (D) Schematic of the 8-bit on-chip calibrated MoS2 DAC. (E) Optical microscope image of an as-fabricated MoS2 DAC. (F) Digital code signal conversion into the analog voltage signal Vw by the DAC. (G) DAC output without and with calibration as a function of the digital code signal.

A single integrated image sensing unit with the above-discussed memory and analog signal processing modules is illustrated schematically in Fig. 4C with an optical microscope image of an as-fabricated unit. An on-chip MoS2 digital-to-analog converter (DAC) module improves the analog signal control of the voltage Vw as applied to the memory module, Ibias, which serves as a universal control for all image-sensing circuits. This is then connected with M2, and VTG3 and can be conveniently updated by refreshing the value of Vw applied to the MoS2 memory module according to specific image quality requirements. In addition, the on-chip DAC module not only isolates off-chip noises but also provides a compatible interface for working with other general integrated circuits (ICs). By tuning the combination of Vw and Ibias, we can realize a dynamic sensing range over 90 dB. With the adaptation process, the dynamic range of MoS2 phototransistors can be further increased ().

The DAC circuit design and layout based on MoS2 TG-FETs are illustrated schematically in Fig. 4D. An optical microscopy image of an as-fabricated module is presented in Fig. 4E. Here, MoS2 TG-FETs Mb0 and Mb1 are the bias current sources, and Md (n = 1 to 8) is a current source. Meanwhile, the calibration transistors Mcal1 and Mcal2 will be discussed in details later. Tuning the W/L ratios of M to M enables their corresponding source currents I to I to be set as I0, 2I0, 4I0, and 8I0 and I1 = 16I0, 32I0, 64I0, and 128I0, respectively. Therefore, the TG-FETs Md1 to Md8 constitute an 8-bit DAC, and each current source can be turned on and off on the basis of the digital code set for switches S1 to S8. Because of the current mirror function, the total output current Iout can be expressed aswhere the state of switch S can be 0 (off) or 1 (on). Accordingly, the DAC has 256 output states, and the value of Iout lies in the range of 0 to 255I0, as shown in Fig. 4F. The extended dynamic output range of the DAC is particularly beneficial for more accurately regulating the output current of the light-sensing and processing units.

However, material and processing issues during the fabrication process introduce nonuniformities in the MoS2 TG-FETs located at different positions on the wafer, which results in mismatches of the transistors and layout. As illustrated in Fig. 4G, these physical nonuniformities introduce corresponding nonuniformities in the output current of the DAC with respect to the designated digital value in the range of 0 to 255. Such current nonuniformity can be compensated by the calibration transistors Mcal1 and Mcal2 in the design, because the gate voltages of the two transistors can be adjusted according to measurement results. As a result, the DAC can provide monotonically and linearly increasing output currents in accordance with the designated digital values, i.e., 0 to 255 (for additional details, see the Supplementary Materials).

Figure 5A shows an optical microscopy image of a fabricated chip composed of 620 pixels. The zoom-in of an individual pixel is presented in Fig. 5B. The input and output current signals can be controlled by two groups of circuits sharing the same sensing, memory, and processing units. All pixels share a single 8-bit MoS2 DAC through a time sequence control circuit. The monolithic chip can exhibit the functions of contrast enhancement and noise reduction to image information when combined with a peripheral control circuit. More details of this chip are provided in the Supplementary Materials. In addition, an optical image of the IC transferred from the sapphire substrate to a flexible polyimide substrate is presented in the inset of Fig. 5A, where the release from the sapphire substrate was facilitated via thermal release tape, and the transfer process was conducted in vacuum.

Fig. 5.

Artificial MVE and noise reduction chip with applications.

(A) Optical microscopic image of a fabricated artificial MVE MoS2 chip on a sapphire substrate. The insets are the image of the MVE chip on a flexible polyimide substrate and the panoramic image of the MVE chip. Images with increasing magnification are also shown, and (B) is a zoom-in image of a single-pixel unit. The modules in red and blue colored boxes share the same circuit design and control current input and output, respectively. (C and D) Dynamic current test sequence of a single pixel under different applied Ibias values. (E) Contrast-enhanced image of the letters FDME before and after image enhancement. (F) Contrast image before and after salt and pepper noise reduction.

A dynamic current test sequence obtained for a single pixel of the MVE chip is presented (Fig. 5C) under three different applied Ibias values (30, 60, and 90 μA), where the low (OFF) and high (ON) output current values correspond to dim and bright environments, respectively. The human visual system requires several minutes to adjust retinal neurons to see objects clearly when moving between dark and bright environments. Figure 5D demonstrates that the output current of our vision sensors can be dynamically adjusted within less than a single millisecond.

The contrast enhancement by the MVE chip is demonstrated in Fig. 5E, where a contrast image of the letters “FDME” is mapped in the XY plane by software according to the output current Z of each pixel in the array. The original output current signals from the MVE chip without image enhancement are presented in the top figure. However, the letter regions of the FDME image represent constant PIN values, such that any inhomogeneity in the output currents of the imaging sensors reflects inhomogeneity in the 2D MoS2 FETs. Accordingly, the image enhancement is conducted by adjusting the value of Vw applied by the DAC module for each imaging sensor unit to ensure homogeneous output currents associated with the letter regions of the FDME image in the pixel array (see the Supplementary Materials).

Similarly, the output currents of the imaging sensors are not only influenced by strong interference or short-pulse signals induced by clock signals but also degraded by unavoidable salt and pepper noise. The original output current signals obtained by the developed MVE chip for an image with salt and pepper noise are presented at the top of Fig. 5F. Salt and pepper noise removal was then conducted by applying a peripheral control circuit based on a median filtering algorithm—a common nonlinear smoothing and signal processing algorithm, which sets the gray level value of each pixel as the average of the gray level values of eight neighboring pixels. The filtering algorithm was implemented by adjusting the value of Vw applied by the DAC module for each imaging sensor unit in the pixel array. The results are presented at the bottom of Fig. 4F (also see the Supplementary Materials, session 8). The DAC and algorithm can successfully reduce the salt and pepper noise.

DISCUSSION

We developed a 619-pixel monolithic chip with physical dimensions of 10 mm by 10 mm for artificial MVE applications based on wafer-scale 2D monolayer MoS2 devices to simultaneously realize light-sensing, memory, processing, and image enhancement functions. The use of analog MoS2 transistor circuits for the imaging sensors offers low-noise and high-sensitivity measurements. The MoS2 analog processing circuits enable the photocurrents of individual imaging sensors to be adjusted dynamically and accurately by a MoS2 DAC. The results demonstrated that the chip featured a high dynamic light-sensing range greater than 90 dB. This vision chip demonstrates the functions through contrast enhancement and noise reduction. Accordingly, the MoS2 vision chip can show the potentials to contribute to future investigations focused on the implantation of flexible, transparent, and biocompatible chips, which provide visual assistance to blind or visually impaired people.

MATERIALS AND METHODS

Synthesis of wafer-scale MoS2

A crucible with sulfur powder (Alfa Aesar; 99.999%) was placed in zone 1 with an appropriate amount of MoO3 powder (Alfa Aesar; 99.95%) set in zone 2 (downstream of the flow in the tube). The distance between the two crucibles was 30 cm. A sapphire substrate was carefully cleaned and placed in zone 2, face down on the crucible containing the MoO3 powder. During synthesis, the temperature in zones 1 and 2 was controlled at 180° and 650°C, respectively. A continuous monolayer MoS2 film was synthesized at atmospheric pressure with 300 standard cubic centimeter per minute of Ar as the carrier gas after 10 min of sulfuration time.

Fabrication of MoS2 devices and ICs

The MoS2 FETs and circuits are fabricated on a wafer-scale sapphire substrate uniformly covered with the CVD-grown MoS2 monolayer film. The contact electrodes were patterned with traditional laser direct writing (MicroWriter ML3), followed by the deposition of a 35-nm Au using electron beam (E-beam) evaporation. The CF4 plasma etching was performed to define the MoS2 channel geometry. SiO2 (2 nm) was deposited as the seeding layer using E-beam evaporation and then annealed in oxygen at 100°C. Then, a 20-nm-thick HfO2 was subsequently grown by atomic layer deposition as the primary dielectric layer. A final lithography and lift-off process was performed to form the TG (35-nm Au), deposited by thermal evaporation. In addition, another lithography and SF6 plasma etching were adopted to form the via holes through the dielectric layer when fabricating the MoS2 circuits.