Scaling quantum approximate optimization on near-term hardware.

The quantum approximate optimization algorithm (QAOA) is an approach for near-term quantum computers to potentially demonstrate computational advantage in solving combinatorial optimization problems. However, the viability of the QAOA depends on how its performance and resource requirements scale with problem size and complexity for realistic hardware implementations. Here, we quantify scaling of the expected resource requirements by synthesizing optimized circuits for hardware architectures with varying levels of connectivity. Assuming noisy gate operations, we estimate the number of measurements needed to sample the output of the idealized QAOA circuit with high probability. We show the number of measurements, and hence total time to solution, grows exponentially in problem size and problem graph degree as well as depth of the QAOA ansatz, gate infidelities, and inverse hardware graph degree. These problems may be alleviated by increasing hardware connectivity or by recently proposed modifications to the QAOA that achieve higher performance with fewer circuit layers.

Introduction

Combinatorial optimization problems are commonly viewed as a potential application for near-term quantum computers to obtain a computational advantage over conventional methods[1]. A common approach to solving these problems uses the quantum approximate optimization algorithm (QAOA)[2], which begins with a “cost” Hamiltonian typically defined aswith real coefficients and that encode a quadratic unconstrained binary optimization problem in the eigenspectrum of C[3]. The QAOA prepares a quantum state on n qubits using p layers of unitary operators, where each layer alternates between Hamiltonian evolution under C and under a “mixing” Hamiltonian composed of independent Pauli-X operators,The state is then measured to yield the n-bit binary string z as a candidate solution to the problem. The angles and are variational parameters chosen to minimize or maximize the expectation value , depending on whether the optimal solution in C is the minimum or maximum value, respectively.

Farhi et al. have argued that QAOA recovers the ground state of C as [2], but the primary interest in QAOA is in reaching high performance with a modest number of layers p that could realistically be implemented on a quantum computer. A significant body of theoretical[4-8], computational[9-13], and experimental[14,15] research has focused on understanding QAOA performance at , mostly on the MaxCut problem with a small number of qubits n, but also for other types of problems[16-18]. These studies have shown some promising results, for example, with QAOA outperforming the conventional lower bound of the GW algorithm for MaxCut on some small instances[19,20]. There have also been a variety of proposed modifications to the algorithm to improve performance[21-28] and solve optimization problems with constraints[29-31]. The results from these and other studies have encouraged research into extending the QAOA to larger and more complex problems.

In contrast to the QAOA studies focused on a small number of variables n, conventional computational methods are capable of handling problem instances with hundreds of variables or more. To assess the usefulness of QAOA it will be necessary to scale to larger and more complex instances where it can be directly compared against these methods on practically relevant problems. A recent study suggests that hundreds of qubits are needed[32] to compete in time-to-solution, while the theoretical and experimental performance in this context are important open questions. Theoretical considerations indicate that the number of layers p will need to scale at least as in some instances, as the locality of the ansatz limits the ability to build global correlations that are needed for globally optimal solutions[33,34]. Classical algorithms have also been developed that outperform QAOA at low p[35,36], further suggesting large p may be necessary to compete with conventional methods. To optimize parameters at large n and p, a variety of computational[37,38] and theoretical[39-44] approaches have been developed and in some cases the theoretical performance has been characterized. With parameter setting strategies at hand, what remains to be seen is how the QAOA will perform in experimental implementations. The prospect of experimentally implementing the QAOA at large n and p raises questions about how quantum computing resources will scale with problem size and complexity, and how noise will influence the behavior of the algorithm.

Here we report on the scaling of resources needed by QAOA on near-term intermediate-scale quantum (NISQ) devices. We show how features of the combinatorial problem and the target hardware influence the total number of gates and measurements required to reach a specified threshold of accuracy. First we consider problem features such as the average degree of the graph defining the problem instance, where is related to the number of non-zero terms in the quadratic unconstrained binary optimization problem. While much of the QAOA literature has focused on problems with small , larger arises naturally in constrained combinatorial optimization problems[45,46]. In addition to , the problem size n and the number of QAOA layers p also contribute to the gate counts and hence the resources required to implement the algorithm. It is furthermore important to consider the constraints that arise in current NISQ hardware due to limited connectivity on the hardware device qubit register, which can require costly gates to transport logical qubits. We show that the interplay between these logical requirements and hardware constraints generate steep scaling in the resources required for high-fidelity implementation of QAOA as n, p, and increase.

Our approach synthesizes optimized circuit representations of QAOA for varying problem sets targeting constrained noisy hardware. We compile circuits in terms of a generic gate set of controlled-not, Hadamard, and rotation gates; these can be translated into native gates for specific hardwares, though we do not include this here. We optimize both the number of gates and the overall performance through placement of the logical qubits and injected gates. Placement and routing are difficult optimization problems and it is not clear a priori how an ideal QAOA instance expressed as Eq. (2) will map to a given hardware[47-50]. To understand the role of hardware connectivity, we synthesized optimized QAOA circuits on scaled versions of each of the connectivity architectures shown in Fig. 1. These planar architectures correspond to contemporary and hypothesized hardware designs. Each architecture has a distinct connectivity defined as the average hardware graph degree , i.e., the average number of distinct two-qubit gate connections per hardware register element (ignoring perimeter elements to give a size-independent ). The architectures range from for the heavy hexagonal lattice in Fig. 1a to for the triangular lattice in Fig. 1d. We quantify the gate counts with respect to and p, and we fit scaling relations to these results.

Figure 1

Hardware connectivity graphs for (a) heavy-hexagon, (b) hexagon, , (c) square, , and (d) triangle, .

Resource counts also give insight into the scalability of the QAOA in the presence of noise. We define a simple noise model for a quantum state traversing a circuit with gate counts estimated from our resource analysis and use this to quantify the reliability of QAOA as it scales to larger and more complex problems. Our analysis complements previous theoretical results describing how noise influences the QAOA cost expectation value, trainability, and eigenvectors of the density operator[51-54]. We compute an upper bound for the number of measurements M that are needed to obtain a single result from the idealized state that would be produced by a noiseless version of the circuit, based on effective gate error rates but without assuming any specific structure or correlations in the noise process. This characterizes the reliability of the algorithm and the expected time-to-solution T, assuming . The results assess the scalability of the QAOA on noisy near-term hardware and the expected influence of and p.

Results

Mapping to hardware

We express the QAOA unitary operators of Eq. (2) in terms of a hardware gate set of Hadamards , Z-rotations , and controlled-not , as described in “Methods”. The gate-to-unitary operator correspondences given there provide the minimal numbers of each type of gate that must be implemented in the algorithm, for example, on fully connected hardware.

It is useful to classify problem instances C in terms of their circuit structure. We define problem graphs G with vertices for each qubit i and edges for each non-zero constant in Eq. (1). Each edge requires a set of two-qubit gates and the total set of edges defines all two-qubit gates that are needed on fully connected hardware. The specific values of the parameters , , , and enter as rotation angles in the circuit, hence all problem instances with the same problem graph have the same circuits up to choices of these angles. When an then a single-qubit gate can be further removed from the circuit, but this does not affect the two-qubit gate structure. We consider all non-isomorphic connected problem graphs with qubits to determine how the circuits scale with the average problem graph degree ; to determine scaling with the number of qubits we assess 3-regular problem graphs with at varying n. On fully connected hardware, the number of gates of each type arewhere is the number of non-zero in Eq. (1) and is an instance-dependent number of gates that can be removed from the first layer of the circuit as they do not affect the initial state[55], see Supplemental Information for details.

However, on hardware with limited connectivity, it is often the case that some of the two-qubit gates cannot be implemented by any initial placement of the logical qubits onto the hardware register. For example, a non-planar problem graph cannot be mapped onto any of the planar registers in Fig. 1. It is therefore necessary to use gates to shuttle logical qubits around the register during execution of the circuit, to realize connections that are not available to the initial qubit placement. There are many potential circuits that can be created and these can result in different total numbers of gates, with up to gates in n circuit layers in the worst case[56,57]. An ideal circuit will minimize the number of gates or circuit depth to minimize the negative impacts of noise in the circuit.

We compute circuits that minimize gate counts for each register architecture in Fig. 1 using an optimization routine. We optimize single layers of the QAOA algorithm as additional layers have the same circuit structure apart from differences in the qubit locations due to gates. These differences can be accounted for by mirroring the circuit implementation of in subsequent layers, so that qubits move back and forth between locations from layer to layer. For an n-qubit problem instance, we use register grids of sizes just larger than , as we found that further increasing the grid size tended to result in larger optimized circuits. Our optimization procedure uses two nested loops. The inner loop is called in the circuit mapping algorithm SABRE[47], which generates a set of random placements of the logical qubits onto the hardware register then optimizes each placement, ultimately returning the final optimized circuit with the smallest depth. For our circuits, we have found that SABRE sometimes yields sub-optimal placements, as it does not recognize the commutativity of the terms in Eq. (2), but instead tries to implement these in the order it is given. We therefore define an outer loop that randomly shuffles these commuting terms, to optimize over varying term orderings. This outer loop decreases the number of gates in our optimized circuits compared to a more basic implementation with SABRE only. For each problem graph, we take our final result from these nested loops as the circuit with the fewest gates. The total number of gates on hardware with limited connectivity with gates iswhere quantifies the average increase in gates per gate, beyond the gates that are needed on fully connected hardware. Each gate is defined as a product of three gates, so in the worst case. In better cases, a gate is placed adjacent to a gate in the circuit and is used to remove a pair of gates. This gives in our accounting. Further details of the implementation, convergence behavior, and performance can be found in Supplemental Information.

Scaling with problem size and degree

We next mapped circuits for each of the 853 non-isomorphic problem graphs at [58]. The results in Fig. 2 show how the number of gates scales with the average problem graph degree at this n across our hardwares with varying . As increases so does the number of edges in the graph, and hence the number of two-qubit gates in each layer of the QAOA algorithm. Greater numbers of gates are needed on average to accommodate these two-qubit gates; in other words, problem graphs that are highly connected (with large ) are likely to have edges that cannot be realized by the initial placement of qubits onto the limited-connectivity registers, thereby requiring SWAP gates. A complementary analysis is given in Supplemental Information in terms of the problem graph diameter, which is the maximum of all minimum distances between qubits in the graph, and is also related to the connectivity of the graph. As the hardware degree increases a greater number of two-qubit gates are available natively on the hardware, so fewer gates are needed. The mean numbers of gates at each and are fit by an empirical linear relation with fit parameters in the figure caption and a root-mean-square-error (RMSE) of 0.58 gates. The small error indicates the empirical relation is successful in providing a unified account of the scaling across problem graphs and hardware architectures at this n.

Figure 2

gate scaling with average problem degree and hardware degree for 7-vertex graphs. The solid line shows the non-linear least squares fit to , with and , with ± indicating the asymptotic standard error of the fit parameters.

Next we consider how the number of gates scales with the size of the problem n. We considered sets of 3-regular graphs with 108 graph instances each at and 60 qubits. The 3-regular problem graphs have three non-zero terms for each qubit i in Eq. (1) and this standardizes as we scale to larger sizes. Three-regular graphs have also been studied with considerable interest in the QAOA MaxCut literature[2,4,9,10,32,39,41] and in a previous experimental demonstration of QAOA[14]. They are appealing targets for near-term hardware since most graphs at the same n have higher average degree , hence we expect them to require more noisy two-qubit gates, due to both the increase in the minimal number of gates in Eq. (5) and also the expected increase in gates following the previous analysis of Fig. 2.

We computed optimized circuit mappings for these 3-regular instances to obtain the key result pictured in Fig. 3, which relates the number of gates to the average hardware degree as the problem size n increases. We fit the data with an empirical curve that is based on counting the number of two-qubit terms that cannot be implemented by the initial qubit placement and assuming the number of gates needed to bring the qubits together for these edge terms increases on average in proportion to the length and width of the hardware grid, see Methods for details. This leads to the empirical relation shown by the solid line in the figurewhere is a fit parameter computed through non-linear least squares and is the asymptotic standard error. Here sets the zero of and represents the maximum problem graph size at which all graphs can be mapped to hardware, for example, for fully connected hardware and . For the triangle lattice in Fig. 1(d), all 3-vertex problem graphs can be mapped directly onto the lattice but the 4-vertex complete graph cannot be, so . For the other hardware lattices, .

Figure 3

Average gate scaling with number of qubits n and hardware degree for 3-regular graphs.

We assess the performance of the empirical formula using the RMSE between the average and the empirical . Across all results in Fig. 3, the RMSE=7.2 gates. The RMSE is strongly influenced by the outliers for the heavy-hexagon array at and , where the empirical formula is up to 16% smaller than the results. These deviations may be related to the bimodal degree structure of the heavy-hexagon array in Fig. 1a, which has a mixture of register elements of degrees two and three, unlike the other constant-degree hardwares. Excluding the results for the heavy-hexagon at and decreases the RMSE to 2.7 gates. We conclude the empirical formula is giving a good fit to the majority of data in the figure, apart from the heavy-hexagon at large n, where the formula gives a looser bound to the observed .

Noisy architecture model and measurement count scaling

We use a simple noise model for our circuits to assess how noise influences the scalability of the QAOA, in terms of the number of measurements M that are needed from a noisy circuit to obtain a single result from the intended noiseless quantum state distribution. This quantifies the reliability of a noisy QAOA circuit in producing the intended output and also characterizes the scaling in the time-to-solution T assuming .

An instance of a QAOA circuit is expressed in terms of a series of gates with ideal unitary evolution operators , with the unitary for the th gate, acting on an initial state . The noisy state produced by the th gate is expressed using a quantum channel as[59]where the Kraus operators give noisy deviations from the intended evolution with probabilities . The final state of the circuit is[54]where is the density operator for the intended pure state , is a density operator composed of all terms with at least one Kraus operator, and is a lower bound to the state preparation fidelity , with equality when . If we assume constant error rates , , and for each , , and gate respectively, thenwhere the N are the corresponding gate counts.

A noisy implementation of QAOA will be effective when it can produce measurement results from the intended state distribution . In the absence of readout errors, a measurement projects the total state onto a computational basis state that is the result of the measurement, with probability . This has a lower bound independent of the specific noise process, apart from the values of the error rates that determine . Summed over all in the support S of , the total probability to obtain any result from the ideal state distribution isWe use this probability inequality to bound the number of measurements that are needed to obtain a single sample from the distribution of the intended state with probability [16,20],

It is useful to consider a few examples. In a theoretical best case of QAOA, the intended state is a single computational basis state that gives the optimal cost value . If we assume that noise does not contribute significantly to the probability for , then and M is close to the upper bound. In more generic cases of interest, the intended state has non-zero probability for a variety of approximately optimal states and the goal is to measure any one of these states. In this case M may be smaller than the upper bound, and potentially much smaller if the probability to measure approximately optimal states is significant for the component. Smaller upper bounds for M might then be obtained using information about the noise process and its expected influence in . However, without detailed information about a specific state and noise process we do not have a way to decrease M below the upper bound, which serves as a generic guide for any possible intended QAOA state and noisy evolution of the type in Eqs. (8)–(9).

We assessed the scalability of the number of measurement samples by computing the upper bound for M for 3-regular graphs at varying sizes n and at QAOA layers, with a probability to sample from the intended state distribution. We evaluate the analytic bound for M in (12), following from earlier analytic expressions in (8)–(10), along with gate counts from our optimized circuits; these calculations are not based on simulations of noisy hardware. We consider 3-regular problem graph instances with gate counts , , and in Eqs. (3), (4), and (6) respectively, assuming all in Eq. (1) so that . We use computed from the empirical formula of Eq. (7) for each hardware architecture in Fig. 1, as the number of additional gates per gate in Eq. (6), in accord with our results at large n from Supplemental Information, and we approximate since when . The in M is then computed from Eq. (10) with assumed error rates of and . For comparison, recent advances in transmon qubits have achieved two-qubit gate error rates of and single-qubit error rates of [60].

Figure 4 shows how this M scales with problem size n. The number of measurements increases exponentially with n at a rate that depends on the hardware degree . The variations in hardware themselves give an exponential divergence in M as the reciprocal hardware degree increases and the hardware becomes less connected (Fig. 4 inset), due to the empirical dependence of from Eq. (7). The hardware dependence is significant at the large n that are required for practical problems. For example, at (vertical dotted line), the number of measurement samples is approximately 20 for fully connected hardware but increases by four orders of magnitude going to the least connected hardware (heavy-hexagon, Fig. 1a). Here exemplifies a nontrivial problem size but is otherwise arbitrary—similar scaling behavior is observed for other large n. Curves similar to Fig. 4 can also be computed for fixed n as the error rates , number of QAOA layers p, or as the problem graph degree increase, see Supplemental Information for details.

Figure 4

The number of measurement samples M to measure a result from the intended state for 3-regular graphs, see text for details. Inset: M diverges exponentially in .

Discussion

Prospects for obtaining a quantum computational advantage with the QAOA are expected to require hundreds of qubits or more to compete against conventional methods on practically relevant problems[18,32]. As the QAOA scales to larger and more complex problems, the number of gates to implement the algorithm on fully connected hardware increases with the problem graph degree and number of qubits n. For sparsely connected hardware additional gates are needed. We computed optimized circuits to determine how the number of gates scales with n and on a variety of real and hypothetical hardware architectures with varying levels of connectivity in terms of the hardware degree . The reciprocal hardware degree , average problem graph degree , and number of qubits n were each found to be important scaling factors in the empirical behavior of . Using a simple noise model with gate counts extrapolated from our circuits we computed the number of measurement samples M from a noisy circuit that are needed to obtain a single measurement from the distribution of an idealized noiseless version of the state with probability . This is a measure of the reliability of a noisy circuit in producing the intended outcome. We argued that M increases exponentially with n, , , the number of QAOA layers p, and the gate error rates . Assuming that M is proportional to the time to solution, this corresponds to an exponential time complexity in each of these factors.

We considered as an example of a nontrivial problem size to compare the number of measurements across different hardwares. Our results show that the number of measurement samples is at this n and for the considered error rates and hardwares. These numbers of measurements should not be difficult to obtain from a quantum computer. However, our parameter choices and problem sets were optimistic in some respects. The assumed error rates were about two orders of magnitude below current state of the art devices[60] and larger error rates exponentially increase the number of measurements. For example, doubling the error rates so that gives for our hardwares. We also assumed 3-regular problem graphs, which have been studied with great interest in the QAOA literature. However, many practically relevant problems use denser problem graphs, for example in constrained optimization problems[18,45,46]. For denser graphs the average degree can scale as n and changes in degree can significantly affect M. For example, using our approach and parameter choices for a 500 qubit problem graph with average degree we obtain on fully connected hardware. For the sparsely connected hardware we consider we do not have a precise scaling relation for on graphs, but if we optimistically use the same relationship we found for 3-regular graphs we obtain at . This is ignoring any dependence of on , which would be significant if our small n observation holds also at large n. A final note is that if more than one measurement is needed from the state with high probability, then this will introduce an additional scaling beyond the M presented here. The numbers of measurements quickly become greater than what can realistically be expected from near-term quantum computers.

We expect the measurement scaling will significantly inhibit the ability to implement the QAOA at scales relevant for quantum advantage. When the QAOA parameters are optimized using measurements from a quantum computer, this optimization will also be greatly inhibited. Parameter optimization has been addressed in some instances using theoretical approaches[9,19,20,37-44], though for generic instances it is unclear if such approaches can be applied. However, even with a good set of parameters the circuit must still be run to obtain the final bitstring solution to the problem, and in our model this requires a number of measurements that quickly becomes prohibitive at scales relevant for quantum advantage. Straightforward attempts to scale the QAOA will face a significant barrier if these scaling problems are not addressed.

Our expectations for performance are based on a general upper bound that is saturated when the noisy and ideal components of the total circuit density operator give distinct measurement results in the computational basis. A vanishing overlap in measurement results is expected when the ideal QAOA circuit prepares a computational basis state, while intermediate superposition states may have non-negligible overlap with the noisy subspace. Further analysis will require details from hardware-specific noise models to determine more precise estimates for how such errors influence M. In addition, there are methods to overcome the measurement count limitations. One approach is to significantly increase hardware connectivity, for example, through non-planar hardware grids. These would overcome the basic inability to directly implement non-planar problem graphs, and detailed accounting of SWAP behavior for such architectures is an important topic for future research. Another possibility is to modify the gate set, for example, using ion-trap quantum computers with globally-entangling Mølmer-Sørensen gates[61] or Rydberg atoms that naturally enforce constraints in some instances of QAOA[62]. Another approach is to modify the QAOA ansatz. This includes introducing additional parameters within layers of QAOA[21], modifying the structure of the ansatz[22-25], modifying the cost function[27], objective function[28], and circuit structure[26]. Such technological and algorithmic advances are likely necessary to reduce the numbers of layers or gates, and hence the accumulated noise, as the QAOA scales to larger sizes.

Methods

We generated circuits using the XACC quantum programming framework[63,64] to map the unitary quantum operators of Eq. (2) to a gate set of Hadamards , Z-rotations , and controlled-NOT gates. To map these circuits to hardware with limited connectivity, we used the Enfield software library[48] and SABRE algorithm[47] implemented within XACC. Details of the implementation, convergence behavior, and comparison with a lower bound for at small n are described in the Supplemental Information.

In terms of our gate set, the unitary operators in Eq. (2) are

Empirical formula for 3-regular graphs

We construct the empirical curve in Eq. (7) by considering how many two-qubit gates cannot be implemented by the initial mapping of qubits onto the register along with the average expected behavior for how many gates are needed to bring qubits together for each of these gates. We begin by separating the edge terms in a mapped problem graph instance into edges that are “satisfied” by the initial placement of qubits on the register, in the sense that the two-qubit gates between and can be implemented in the initial placement, and edges that are “unsatisfied,” in the sense that gates are needed to bring the qubits and together to implement their two-qubit gates. Our approach is to express the total number of gates as , where is the number of gates that are used in the circuit to bring qubits and together to implement the two-qubit gates for u.

Some care is needed to define the to give a consistent total . Each gate moves locations of two qubits and hence can contribute to two terms and ; one approach is to allow for fractional values in the , for example, values of 1/2 in and when a gate moves two qubits that help to satisfy u and . Another consideration is that a series of gates may be implemented before the gates for a given u, while along the way the gates that are relevant for u may also allow for implementations of two-qubit gates for a variety of other . We could then assign fractional values to each of the based on which qubits are moved by the series of gates and which unsatisfied edges they contribute to, such that . A final consideration is that sometimes the circuits will qubits that are in initially satisfied edges s before the two-qubit gates for those edges are implemented. Although additional gates are sometimes used in these cases for the satisfied edges s, these gates are only needed because there were initially unsatisfied edges u which began a series of gates earlier in the circuit, so it is reasonable to systematically assign the gates for these s to the . Although the calculation of the is somewhat complicated by these considerations, by design the total must always sum to . This can be expressed as an average , where is the total number of unsatisfied edges and is the average number of gates per unsatisfied edge. The is determined solely by the initial placement of qubits onto the register, while the average . We argue for the behavior of these terms in determining and the empirical fit curve of Eq. (7).

For each hardware architecture and circuit, we computed the number of two-qubit edge terms that cannot be implemented directly on the hardware with the initial qubit placement. The for each hardware are found to scale as , where is a threshold size at which all graphs can be mapped directly to the hardware. The quantity sets the zero of and hence , for example, on fully connected hardware so and no gates are needed. The rationale for the n dependence is that, on average, the number of unsatisfied edges increases linearly with the total number of edges, for the 3-regular graphs. The linear relations for each individual hardware are shown in Supplemental Information. They can be related to one another with a factor that decreases the number of unsatisfied edges when more two-qubit connections are available on the register. This gives a single unified relationship for all our hardware architectures as shown in Fig. 5. This motivates and accounts for a factor in the empirical formula in Eq. (7).

Figure 5

The number of initially unsatisfied edges in the initial qubit placement at each n and for 3-regular graphs.

The remaining factor in the empirical of Eq. (7) relates to the average numbers of gates per unsatisfied edge . We can rationalize the dependence by considering how many gates are needed to bring qubits together to satisfy an edge u, based on the typical distance between qubits on the approximately hardware grids with . We begin by considering uniform random placements of logical qubits along a single dimension of length . The probability for the first qubit to be at location i is , the probability for the second qubit to be at any other location j is , and the average distance between the qubits is . This scales approximately as . If qubits are placed uniformly at random in two-dimensions and they move along each dimension separately, for example in the square hardware lattice of Fig. 1c, then the total distance is twice the distance in a single dimension and this again scales as . In reality the qubit placements are optimized instead of uniformly random, but still the length scales as in each dimension and this gives some justification for the appearance of in . Finally, we need to account for a factor to obtain the desired relation . We rationalize this factor by considering that fewer gates are needed to move a qubit from one location to another when there are more connections on the register, for example, in the triangle lattice some diagonal movements are allowed on the planar grid and we expect this to decrease the number gates that are needed. We incorporate this through a factor such that . Combined with the previous analysis of , we have , giving the empirical formula of Eq. (7).

Supplementary Information.