Novel Modeling Approach to Analyze Threshold Voltage Variability in Short Gate-Length (15-22 nm) Nanowire FETs with Various Channel Diameters.

In this study, threshold voltage (Vth) variability was investigated in silicon nanowire field-effect transistors (SNWFETs) with short gate-lengths of 15-22 nm and various channel diameters (DNW) of 7, 9, and 12 nm. Linear slope and nonzero y-intercept were observed in a Pelgrom plot of the standard deviation of Vth (σVth), which originated from random and process variations. Interestingly, the slope and y-intercept differed for each DNW, and σVth was the smallest at a median DNW of 9 nm. To analyze the observed DNW tendency of σVth, a novel modeling approach based on the error propagation law was proposed. The contribution of gate-metal work function, channel dopant concentration (Nch), and DNW variations (WFV, ∆Nch, and ∆DNW) to σVth were evaluated by directly fitting the developed model to measured σVth. As a result, WFV induced by metal gate granularity increased as channel area increases, and the slope of WFV in Pelgrom plot is similar to that of σVth. As DNW decreased, SNWFETs became robust to ∆Nch but vulnerable to ∆DNW. Consequently, the contribution of ∆DNW, WFV, and ∆Nch is dominant at DNW of 7 nm, 9 nm, and 12, respectively. The proposed model enables the quantifying of the contribution of various variation sources of Vth variation, and it is applicable to all SNWFETs with various LG and DNW.

1. Introduction

Gate-all-around (GAA) silicon nanowire field-effect transistors (SNWFETs) are considered as a viable option for future device architecture due to their adequate gate-controllability with GAA structures [1,2,3]. However, ultrascaled SNWFETs suffer from severe threshold voltage (Vth) variation because the device-to-device variation increases with the decrease in the effective channel width (Weff) and gate-length (LG) [4,5]. According to previous studies, random variations such as metal gate granularity (MGG), line edge roughness (LER), and random dopant fluctuation (RDF) cause Vth variation in ultrascaled GAA transistors [6,7,8,9,10]. Additionally, the Vth variation is also induced by the process variations such as junction gradient and channel thickness variation [11,12,13,14,15,16,17].

Therefore, several simulations and models have been recommended to analyze the contribution of multiple sources to Vth variation. First, technology computer-aided design (TCAD) simulations are suitable for analyzing the influence of variation sources, but it is difficult to predict the cause of variation inversely from measured Vth variation [6,7,8,9,10]. Second, simulation program with integrated circuit emphasis (SPICE)-based models can be applied to analyze the variation sources of measured Vth variation, but it consumes time and makes an error because all devices should be calibrated [15]. Last, models based on the error propagation law have been proposed [16,17]. These modeling approaches enable extraction of the contribution of each variation source to the standard deviation of Vth (σVth) fast and accurately because they directly model σVth. However, the error propagation law-based model to analyze the Vth variability of SNWFET has not been suggested.

Previously, Vth variability in SNWFETs was investigated considering various LG using a SPICE-based model [15]. However, the study did not consider the effect of channel dopant concentration (Nch) variation and nanowire diameter (DNW) change. Furthermore, although DNW influences Weff, electrostatics, and quantum effect [18], the DNW tendency of Vth variability in SNWFET with short LG has not been thoroughly investigated.

Therefore, in this study, we quantitatively analyzed the sources of Vth variation in SNWFETs with short LG (15–22 nm) and multiple DNW (7, 9, 12 nm). A novel modeling approach based on the error propagation law is proposed to estimate the contribution of multiple variation sources to the Vth variability. The dominant variation source of Vth variation is analyzed for each DNW by using the proposed model. Additionally, the standard deviation of Nch (σNch) and DNW (σDNW) according to LG is presented.

2. Device Structure and Modeling Methods

2.1. Structure and Possible Vth Variation Sources of SNWFETs

Figure 1 depicts the schematic and Vth variation sources of SNWFETs, fabricated using the same process flow reported in [19,20]. The SNWFETs adopted Mid-gap TiN metal gate, gate oxide thickness (tox) of 3.4 nm, and (110) channel direction. The gate and nanowire trimming process was used to obtain LG varying from 15 to 22 nm and DNW of 7, 9, and 12 nm. In this process, DNW variation (∆DNW) was caused by LER occurred at the nanowire (NW) edges and under- or over-etching of the NW [21]. MGG occurred in the TiN metal gate and generated the metal work function variation (WFV) [22]. The transmission electron microscope (TEM) image shows many grain boundaries exist in the TiN metal gate of the SNWFETs [19]. Although the SNWFET is fabricated with an undoped channel, the source/drain (S/D) dopants diffuse into the channel with short LG [18,23]. Consequently, Nch variation (∆Nch) was caused by RDF, the S/D dopant implant, annealing, and SiGe strain variation [8,9,10].

Figure 1

Schematic of the silicon nanowire field-effect transistor (SNWFET) and possible Vth variation sources.

Figure 2a depicts the ID–VG characteristics of SNWFETs with LG = 15 nm and DNW = 7 nm at a drain bias of 0.05 V. About 50 samples were measured per device condition. Here, Vth was extracted at ID = 10−7 × πDNW/LG using the constant current method. The fluctuation of extracted Vth shows the process and random variation affect the physical characteristics of SNWFETs. Figure 2b illustrates a quantile plot of Vth for each DNW in SNWFETs with an LG of 15 nm, which shows the distribution of Vth. The distribution of Vth predominantly follows the theoretical normal distribution for all device conditions, which indicates that sufficient Vth values were obtained to analyze σVth.

Figure 2

(a) Vth fluctuation in ID−VG of silicon nanowire field-effect transistors (SNWFETs) with LG = 15 nm and DNW = 7 nm. Vth is directly extracted using the constant current method at ID = 10−7∙πDNW/LG. (b) Quantile plot of Vth of the SNWFET with LG = 15 nm.

Figure 3 is the Pelgrom plot of σVth in SNWFETs for each DNW, showing the trend of σVth as channel area changes. The slope of the Pelgrom plot, defined as the Pelgrom coefficient (Avt), represents the effect of random variation [4]. The y-intercept of the Pelgrom plot is also observed, indicating the effect of the process variation and short channel effect [12,24]. Remarkably, the values of Avt and y-intercepts differed for each DNW, and the σVth is smallest in median DNW of 9 nm. We anticipated that this result implies a trade-off relationship between the various variation sources. Hence, a novel modeling approach is proposed to analyze the contribution of each variation source to σVth.

Figure 3

Pelgrom plot for Vth variation of the silicon nanowire field−effect transistors (SNWFETs).

2.2. Proposed σVth Model of SNWFETs

Figure 4 shows the proposed modeling flow to analyze the contribution of WFV, ∆Nch, and ∆DNW to σVth. To model σVth, we started from a physical model for Vth of SNWFET, as follows [25,26]: where ΦM denotes the work function of the TiN gate metal; ΦS represents the work function of silicon channel calculated as χsi − Eg/2 + kT/q∙ln(Nch/ni), where χsi is the electron affinity and Eg is the band gap of silicon; rnw indicates the radius of NW; and represent the dielectric constant of silicon and oxide, respectively; h denotes the Planck constant; and m* indicates the effective mass of an electron. Cox represents the oxide capacitance calculated as 2πεox/ln(1 + tox/rnw). The possible Vth variation sources in Equation (1) are ΦM, Nch, DNW, and tox variations. Among them, tox is not considered because its variation and effect are very small and negligible [11,12,27]. Although the variation of effective channel length (Leff) is not considered directly, Nch variation partially represents Leff variation because S/D dopant diffusion and LG variation change Nch and Leff simultaneously.

Figure 4

Flowchart of the proposed σVth modeling process.

Hence, considering three identical variation sources of WFV, ∆Nch, and ∆DNW, σVth can be expressed based on the error propagation law as

To analyze σVth using Equation (2), the sensitivity of Vth against variation sources and their standard deviation should be extracted. First, the standard deviation of metal work function (σΦM) can be estimated by the existing WFV model for SNWFETs, as follows [22]: where RGG is the ratio of average grain size to the gate area, SL is the sensitivity of σVth against RGG, and G is the grain size of the metal gate. Here, Gsize can be estimated from a TEM image of the TiN metal gate of SNWFETs. SL of SNWFETs can be obtained from previous research based on TCAD simulation [22].

Second, the sensitivity of Vth against ∆Nch and ∆DNW can be obtained by calculating the partial differentiation of Equation (1), as follows: where k denotes the Boltzmann constant. Here, Nch can be extracted where Equation (1) best fits to measured Vth. Finally, σNch and σDNW are extracted when Equation (2) best fits the square of the measured σVth.

The proposed model obtains the Vth sensitivity against ∆Nch and ∆DNW through simple calculation and extracts the standard deviation of each variation source by fitting the model to the measured σVth. Therefore, the contribution of multiple variation sources to σVth can be directly and quickly modeled and analyzed using the proposed model without any TCAD or SPICE simulation. Furthermore, the proposed Vth modeling flow is expected to be applied to analyze σVth in most multigate devices with various LG and channel thicknesses.

3. Results and Discussion

3.1. Vth Modeling Results of SNWFETs

Nch is extracted where Equation (1) fitted Vth versus DNW with high accuracy in SNWFET with LG of 15 nm, as shown in Figure 5a. Figure 5b shows Nch increases as LG decreases because more dopant diffused to the center of the channel from S/D even with the same S/D junction gradient. The sensitivity of Vth against ∆Nch and ∆DNW was calculated by substituting Nch and other parameters in Equations (4) and (5).

Figure 5

(a) Measured (black dots) and modeled (blue line) values of Vth as a function of DNW. (b) Extracted Nch as a function of LG.

3.2. Vth Standard Deviation Modeling Results of SNWFETs

3.2.1. Extraction of Gsize and WFV of SNWFETs

Gsize should be determined from the TEM image of the TiN metal gate of the SNWFET to analyze WFV. Figure 6a shows a schematic of the grain boundaries based on TiN metal gate TEM image [19]. Gsize was measured as the average of values obtained by dividing the length of TiN metal in the TEM image (LTEM) by the number of intersections between grain boundaries and horizontal lines (Nint), as follow [28]: where Nline is the number of horizontal lines. The distance between the lines was set to 5 nm, as shown in Figure 6a. Consequently, Gsize measured using Equation (6) was 11.8 nm in SNWFETs. According to previous research, the value of SL is 105 V/nm in SNWFETs [22]. σΦM was calculated by putting obtained Gsize and SL into Equation (3), and Figure 6b shows σΦM as a function of the square root of the channel area. Interestingly, the trend and value of the slope in Figure 6b (AWFV) are very similar to Avt for each DNW. It means WFV induced by MGG is the dominant random variation component of Vth variation in the SNWFETs.

Figure 6

(a) Grain boundaries estimated from [19] and red horizontal lines to estimate Gsize of TiN metal gate of SNWFETs. (b) Pelgrom’s plot only considering work function variation (WFV) by metal gate granularity (MGG).

3.2.2. The Contribution of Variation Sources to σVth for Each DNW

Figure 7 shows that Equation (2) accurately fitted the measured σVth with the relative root mean square error of 0.3% where σNch = 1.11 × 1018 cm and σDNW = 0.743 nm. WFV and DNW are slightly correlated because DNW is included in Equation (3), which can affect the modeling accuracy. However, assuming the occurrence of ∆DNW of 0.743 nm, the possible WFV fluctuation is only by 2.4% of total σVth and does not change the DNW tendency of σVth induced by each variation source. The DNW tendency of σVth can be explained by the different contributions of the three variation sources, which are represented using pink (WFV), red (∆Nch), and green (∆DNW) lines in Figure 7. The modeling results are shown considering LG = 15 nm; however, the model was also applied to SNWFET with other LG, and the modeling accuracy and trend of each variation sources are very similar.

Figure 7

Model fitting results (blue line) considering WFV (pink line), ∆Nch (red line), and ∆DNW (green line) for the measured value of squared σVth (black dots). The model fits were extrapolated for DNW of 6 and 15 nm (dashed line).

Although AMGG decreases when DNW decreases, the contribution of WFV increases owing to the decrease in the channel area. As DNW decreases, SNWFETs become robust to ∆Nch-induced Vth variation. This is because the influence of depletion charge and surface potential is reduced proportional to because of the improvement in gate-controllability, as shown in Equation (4). Conversely, SNWFETs become vulnerable to ∆DNW-induced Vth variation because the sensitivity of Vth to quantum effect is proportional to 1/, as indicated in Equation (5). Consequently, the contribution of ∆DNW, WFV, and ∆Nch is dominant when at DNW of 7 nm, 9 nm, and 12, respectively.

3.2.3. The Tendency of σNch and σDNW as LG Changes

Figure 8 shows both σNch and σDNW increases as LG decreases. This result means that RDF and LER occur because their influence increases as the device dimension decreases. However, the degree of σNch and σDNW increase is small, about 5%, as LG decreases from 22 to 15 nm. In addition, we already verified WFV by MGG is the dominant random variation component of Vth variation in Section 3.2.1. Hence, most ∆Nch and ∆DNW originated from process variation sources, which causes non-zero y-intercept in Figure 3.

Figure 8

Extracted σNch (black line) and σDNW (blue line) as function of LG.

4. Conclusions

The contribution of WFV, ∆Nch, and ∆DNW in Vth variation of SNWFET was quantitatively analyzed for each DNW using the novel modeling approach. The sensitivity of WFV against the channel area is similar to that of σVth. As DNW decreases, SNWFETs became robust to ∆Nch but vulnerable to ∆DNW. The dominant variation sources differed for each DNW. Hence, the strategy to improve the variability of SNWFETs should be different for each DNW. Furthermore, with slight modifications, the proposed modeling approach and results are expected to be used in most multigate devices, including FinFET and nanosheet FET.