Layer-resolved release of epitaxial layers in III-V heterostructure via a buffer-free mechanical separation technique.

Layer-release techniques for producing freestanding III-V epitaxial layers have been actively developed for heterointegration of single-crystalline compound semiconductors with Si platforms. However, for the release of target epitaxial layers from III-V heterostructures, it is required to embed a mechanically or chemically weak sacrificial buffer beneath the target layers. This requirement severely limits the scope of processable materials and their epi-structures and makes the growth and layer-release process complicated. Here, we report that epitaxial layers in commonly used III-V heterostructures can be precisely released with an atomic-scale surface flatness via a buffer-free separation technique. This result shows that heteroepitaxial interfaces of a normal lattice-matched III-V heterostructure can be mechanically separated without a sacrificial buffer and the target interface for separation can be selectively determined by adjusting process conditions. This technique of selective release of epitaxial layers in III-V heterostructures will provide high fabrication flexibility in compound semiconductor technology.

INTRODUCTION

Heterogeneous integration of materials is one of the important processing technologies for emerging electronic and optoelectronic applications such as monolithic three-dimensional (3D)–integrated circuit (IC) chips and high-performance flexible devices based on single-crystalline inorganic semiconductors. The cointegration of heterogeneous materials with dissimilar electrical and optical properties enables advanced device technologies with a broad spectrum of functionalities beyond the limitations of a single-material nature. In particular, the cointegration of compound semiconductor devices and Si-based ICs can offer an effective pathway for overcoming Si’s poor light-emitting properties and ultimately realizing the monolithic integration of photonic circuits with complementary metal-oxide semiconductor (CMOS) ICs on a single chip (–). The simplest approach to this cointegration is to directly grow epitaxial layers of compound semiconductors on desired regions of an Si substrate. The compound semiconductors required for the cointegration with Si are typically GaAs- or InP-based III-V alloys such as InGaAs and InGaAsP, which are used for the fabrication of light sources and photodetectors in Si photonics (). However, it is extremely difficult to epitaxially grow high-quality heterostructures composed of these compound semiconductors on an Si substrate because of a large lattice and thermal expansion coefficient (TEC) mismatch with Si(100) (, ). For instance, the lattice/TEC mismatch of GaAs and InP with Si is approximately 3.9/128.1 and 8.0/73.1%, respectively, which induces a large density of dislocations and excessive strain upon the heterostructures (, ).

As an approach without direct heteroepitaxy, layer release/transfer techniques for separating a thin layer of single-crystalline compound semiconductors and subsequently bonding it to arbitrary substrates have been actively developed at the industrial scale because this approach can enable a versatile combination of various semiconductors for heterointegration without the limitations of lattice and TEC mismatch. One of the commonly used processes is epitaxial lift-off (ELO) and its variant techniques. The most typically used ELO process is a chemical lift-off technique. For this process, a chemically weak layer is first grown as a sacrificial buffer during a heterostructure epitaxy step, and the weak layer is then selectively etched away for the release of the epitaxial layers on top of the buffer (–). Although this process has been widely used to fabricate thin, flexible, and 3D-integrated structures, it can only be applied to epitaxial heterostructures with extremely high etching selectivity between the sacrificial buffer and other layers and has limitations in high-throughput wafer-scale processes because of the slow lateral etching rate of the sacrificial buffer (). Another type of the ELO process is a mechanical lift-off technique. For this process, a mechanically weak defective or porous sacrificial buffer is first formed within a heterostructure, and the sacrificial buffer is then physically broken for the layer release (, ). This is a much faster process than the chemical lift-off technique. However, the formation of the mechanically weak buffer in the heterostructure makes the growth process very complicated and limits the crystal quality of single-crystalline epitaxial layers grown on the buffer. In addition, this process is also allowed only for the limited scope of III-V materials and epitaxial structures. Recently, a graphene-assisted layer release/transfer technique has been suggested (–). This technique is based on remote epitaxy allowing the growth of single-crystalline compound semiconductor layers on a graphene buffer, which thereby enables facile layer release from the graphene surface because of its weak van der Waals bonding. Although this technique has been widely applied for the cointegration of various heterogeneous materials, for industrial adoption, it is still necessary to improve the processes for the growth and transfer of large-scale defect-free graphene layers because the process yield depends on the quality of transferred one- or few-monolayer graphene ().

As an alternative approach without using a sacrificial buffer, a mechanical separation technique called thickness-controlled spalling has been actively studied because it enables the fast and kerf-less release of wafer-scale semiconductor layers through a relatively simple and low-temperature process (, –). In this process, a thin single-crystalline semiconductor layer is mechanically released by the stress induced from a stressor film (typically, Ni) deposited on the substrate. Because the spalling process of semiconductors relies on the mechanical separation of crystal planes in the single-crystalline substrates, a thin-layer release is possible without a sacrificial buffer. Moreover, the thickness of the released layer can be controlled from hundreds of nanometers to tens of micrometers by adjusting the thickness and stress of the Ni film. On the basis of these advantages, the thickness-controlled spalling technique has been applied to a wide range of materials from elemental semiconductors (, –, , ) to compound semiconductors (, –). In particular, this technique has been effectively used in device fabrication with a thin layer of elemental semiconductors (Si and Ge). For instance, flexible logic and memory ICs based on sub–30-nm CMOS technology (–), wearable/stretchable sensors (, ), and thin-film photovoltaic cells (–) for flexible applications have been demonstrated using Si or Ge spalling processes. In practice, the greater potential of this buffer-free mechanical separation technique is derived from the layer release of compound semiconductors, which enables the versatile heterointegration of III-Vs and Si. However, it is known that this technique has a critical issue for applying to III-V semiconductors. In contrast to elemental semiconductors, the spalling process for zinc-blende (100) compound semiconductors such as GaAs- or InP-based III-Vs leaves zigzag corrugations on the surface of the released III-V layers and substrates because of the undulating crack propagation along the {110} planes (, –). It has been reported that the height and pitch of the corrugations can be as large as several to tens of micrometers (, ). This is a substantial problem that limits practical applications of this buffer-free mechanical separation technique to cointegration of III-V and Si devices because the nonflat surface impedes the subsequent transfer of the released layer and the continuous reuse of the substrate.

In this study, we propose a layer-resolved mechanical separation technique that can precisely release target III-V epitaxial layers from a single-crystalline heterostructure without a sacrificial buffer. This technique is based on mechanical exfoliation at the epitaxial interface of a heterostructure and allows the release of single-crystalline III-V layers with an atomically flat surface. To demonstrate this technique, we epitaxially grow a lattice-matched heterostructure with multiple InP/InGaAs junctions on an InP(100) wafer and show that the epitaxial layers can be released at a specific junction of the heterostructure. Furthermore, we demonstrate that the target junction for separation can be selectively determined by controlling the strain energy induced by the Ni stressor film. Structural characterizations based on energy-dispersive x-ray spectroscopy (EDS), Raman spectroscopy, and atomic force microscopy (AFM) measurements prove that layer release occurs precisely at junctions between the InGaAs and InP epitaxial layers and the surface of the released layers is atomically flat. Last, we confirm the effect of the proposed layer-release process on crystal and material quality by measuring high-resolution x-ray diffraction (XRD) and photoluminescence (PL) characteristics after the transfer of the released InP/InGaAs epitaxial layers onto an Si substrate.

RESULTS

Layer release of III-V compound semiconductors

Thickness-controlled spalling technique and its mechanism for layer release of single-crystalline semiconductors are summarized in the Supplementary Materials (fig. S1 and note S1). As reported in the literature, it can be observed that the spalling process for zinc-blende III-V(100) compound semiconductors such as GaAs(100) and InP(100) leaves zigzag corrugations on the surface of the released layers, unlike the spalling process for elemental semiconductors. The origin of the formation of the corrugations in III-V(100) spalling could be explained by undulating crack propagation along the {110} planes (, , ), as shown in Fig. 1A. In the spalling of (100) semiconductors, the (100) plane is oriented parallel with the “local symmetry plane” where the mode-II stress intensity factor (KII, in-plane shear mode) is zero (i.e., KII = 0). However, in the case of III-V(100), the crack is inclined to deviate from the local symmetry plane to grow on the (110) plane because the surface energy of the (100) plane is considerably higher than that of the (110) cleavage plane (, ). As the crack grows off from the local symmetry plane, the magnitude of KII grows from 0, and KII at the crack tip evolves to act in a way of stabilizing the crack path (i.e., inducing the crack to grow back toward the local symmetry plane with a decrease in its magnitude). When KII decreases back to 0, the crack deviates from the local symmetry plane again to grow on the plane. This directional change of the crack is repeated alternatively with respect to the local symmetry (100) plane. Thus, after successive directional changes of the crack, the periodic zigzag corrugation is formed at the released surface. To investigate the surface structure of the released III-V(100) layers, we fabricated thin GaAs and InP layers with various layer thicknesses. First, as expected from the suggested theory, there was correlation between the peak-to-peak height and pitch of the zigzag corrugations on the released layers. Half of the zigzag pitch was directly proportional to the zigzag height over the entire released region, as shown in Fig. 1B; this indicates that the facet of the corrugation is composed of {110} cleavage planes. This result supports the idea that the corrugations originate from the surface-energy contrast between the (100) and (110) crystal planes. Second, we observed that the height of the zigzag corrugations was dependent on the released-layer thickness. In our study, the zigzag height was approximately 1.2 times larger than the released-layer thickness in its range from 2 to 13 μm (Fig. 1C). This result suggests one simple approach to minimizing zigzag corrugations, that is, releasing the III-V(100) layer as thin as possible. However, the practical problem is that the minimum spalling depth (released-layer thickness) guaranteeing the reliability of this process is typically limited to 1 to 2 μm (, ). When the Ni film is too thin, it is difficult to initiate a crack. Last, the local nonuniformity of the film stress and undesirable external force can cause nonuniform crack propagation. Thus, it may be difficult to remove the surface corrugation by engineering the process conditions, and this issue limits practical applications of the spalling process because of the difficulty with the transfer of the released III-V layers and the continuous reuse of substrates (fig. S2 and note S2).

Fig. 1.

Formation of zigzag corrugations in a bulk III-V(100) and layer-resolved mechanical separation for III-V heterostructures.

(A) Crystallographic planes of zigzag corrugation formed in the spalling of a bulk III-V(100) semiconductor. The corrugation originates from undulating crack propagation along the {110} planes because of the surface-energy contrast between the (100) and (110) crystal planes. (B) Correlation between the height and half-pitch of the zigzag corrugations on the released GaAs(100) and InP(100) layers, confirming that the facets of the corrugations are composed of {110} cleavage planes. (C) Peak-to-peak height of the zigzag corrugations increases along with the thickness for both the released GaAs(100) and InP(100) layers. (D) A schematic of the proposed layer-resolved mechanical separation technique. By matching the location of the local symmetry plane (where KII = 0) with a specific interface of an epitaxial heterostructure, a crack can propagate straightly along the junction between heteroepitaxial layers because of the relatively weak surface energy at the interface. The target junction for layer release in the heterostructure can be selectively determined by controlling the strain energy induced by the stressor film.

Layer-resolved mechanical separation technique for III-V heterostructures

As an alternative approach, based on the results and mechanism of the III-V(100) spalling, we designed a layer-resolved mechanical separation process for III-V heterostructures. The zigzag corrugations originate from the fact that the surface energy of the local symmetry (100) plane is significantly higher than that of another crystal plane, i.e., the (110) plane. This means that the spalling of III-V compound semiconductor layers with a flat surface and a uniform thickness may become possible if we can find a condition in which the surface energy of the local symmetry plane is less than that of the (110) plane. To achieve this condition, our approach is to match the location of the local symmetry plane (i.e., spalling depth) to a covalent-bonded epitaxial interface in a III-V heterostructure composed of multiple epitaxial layers. The reason is that the surface energy (i.e., crystal binding energy) of an epitaxial interface in III-V heterostructures can be reduced by the misfit-induced strain energy. In cases of lattice-mismatched heterostructures, a strong misfit strain is induced between the heteroepitaxial layers, and furthermore, localized dislocations and defects are often introduced into the crystals near the epitaxial interface (–, ). Even in lattice-matched heterostructures, it is known that an abruptly inverted heteroepitaxial interface contains at least one or few monolayers of undesirable lattice-mismatched III-V alloy, which is induced by phase intermixing because of interdiffusion of atoms or memory effects of precursors (–). For instance, compressive-strained InAs and InAsP or tensile-strained InGaP layers are formed at the heteroepitaxial interface of the lattice-matched InP/In0.53Ga0.47As heterostructure (–). Thus, as the localized misfit strain energy is introduced at the epitaxial interface, the surface energy of the (100) plane aligned with the strained interface layers can be reduced to less than that of the (110) plane, and thereby, the (100) interface plane becomes preferable to the (110) plane for the layer release in spalling processes. The reduction in crystal binding energy at a heteroepitaxial interface of lattice-matched heterostructures can also be predicted from a simple binding-energy calculation on the basis of density functional theory (see fig. S3 and note S3 for calculation results of the representative lattice-matched III-V heterostructures, InP/InGaAs, and GaAs/InGaP).

Because III-V semiconductors are typically grown as an epitaxial heterostructure rather than as a bulk for device applications, if this process is viable, then it would enable a versatile III-V spalling technique capable of selectively releasing single-crystalline III-V layers of interest from a heterostructure. The concept of this process is illustrated in Fig. 1D. Crack propagation is not straight when the local symmetry plane is located in the bulk substrate; however, if the location of the local symmetry plane is matched to one of the heterointerfaces (i.e., junctions between heteroepitaxial layers) that are covalently bonded, then layer release can occur at a specific junction via a straight crack propagation along the relatively weak local symmetry plane. Furthermore, the target interface to be separated in the multiple epitaxial layers can be selectively determined by controlling the strain energy from the stressor film.

To demonstrate the proposed layer-resolved mechanical separation technique, we first grew a III-V heterostructure composed of lattice-matched multiple InP/In0.53Ga0.47As epitaxial layers on an InP(100) wafer using a metalorganic chemical vapor deposition (MOCVD) system. This structure is one of the commonly used heterostructures for fabricating a near-infrared–sensitive p–i–n photodiode (, ). The epitaxial layer structure is shown in Fig. 2A. To verify the layer selection capability of the proposed technique, we designed process conditions to set the local symmetry plane at three different locations in the heterostructure. The first process condition corresponds to that in which layer release occurs in the bulk substrate (process I). The other process conditions are designed to match the location of the local symmetry plane to one of the interfaces between the heteroepitaxial layers (processes II and III). The locations of the local symmetry planes in processes I, II, and III are denoted in Fig. 2A. In process II, the local symmetry plane is set to the junction between the n-InGaAs and n-InP layers. In process III, the local symmetry plane is set to another junction, the epitaxial interface between the n-InP and i-InGaAs layers. To establish detailed experimental conditions for the three layer-release processes, it is essential to estimate the correlation between the spalling depth and the strain energy determined by the thickness and stress of the Ni stressor film. Thus, we first measured the internal stress of the Ni film with varying Ni thicknesses using a multibeam optical sensor system () and calculated the strain energy accumulated in the substrate as a function of the Ni thickness (Fig. 2B). This result shows that the strain energy can be controlled by adjusting the Ni thickness. Then, the estimated spalling depth was calculated as a function of the Ni thickness using an analytical model based on delamination theory (, –). In this model, the spalling depth is determined from the thermodynamic equilibrium condition in which the total strain energy accumulated in the Ni film and the released layer is balanced with the crystal binding energy of a (100) plane (see fig. S4 and note S4 for details of the analytical model and calculation procedure).

Fig. 2.

Selection of target junctions for layer release in an InP/InGaAs heterostructure by controlling the strain energy induced by the Ni stressor film.

(A) A schematic of the epitaxial heterostructure with multiple InP/InGaAs junctions used in this study. Processes I, II, and III denoted in the schematic indicate layer-release processes with three different locations of local symmetry planes (dashed red lines). Process I corresponds to a process condition for layer release in the bulk substrate. Processes II and III correspond to process conditions that are designed for the release of the epitaxial layers at different InP/InGaAs junctions. (B) Internal stress of the Ni film and the strain energy accumulated in the substrate as a function of the Ni thickness, showing that strain energy can be controlled by adjusting the Ni thickness and stress. (C) The estimated spalling depths of the layers as a function of the Ni thickness (red solid line) calculated from an analytical model on the basis of the thermodynamic equilibrium condition between the stress-induced strain energy and the crystal binding energy. Dots in the plot indicate the empirical results for processes I, II, and III, showing good agreement with the estimates obtained by the analytic model. (D) Cross-sectional scanning electron microscopy (SEM) images of the released layers and the remaining substrates after processes I, II, and III. These show that the epitaxial layers released at the InP/InGaAs junctions are flat and the target junction for layer release can be controlled by the strain energy induced by the Ni stressor film, whereas the surface of the layer released in the InP bulk exhibits the zigzag corrugation.

The calculated spalling depth is shown by the solid line in the plot of Fig. 2C. From this analytical calculation, we estimated the Ni thickness for processes II and III to be ~3.5 and 3 μm to match the spalling depth to two different junction depths. For process I, we set a thicker Ni thickness (7 μm) to guarantee that the layer release occurs in the InP bulk. On the basis of these estimates, we released the III-V epitaxial layers using the Ni stressor films with various Ni thicknesses and found out that release of the layers with a flat and uniform surface at specific junctions was possible when the Ni thickness was 3.2 μm for process II and 2.8 μm for process III. When we deposited 7-μm-thick Ni, the spalling occurred in the bulk with a released-layer thickness of 28 μm, as expected. The released-layer thicknesses (spalling depths) in processes I, II, and III are shown by the dots in Fig. 2C. The empirical results showed good agreement with the estimates by the analytic model. The cross-sectional scanning electron microscopy (SEM) images of the released layers and the remaining substrate after the three processes are shown in Fig. 2D. (The SEM images obtained with different magnifications are shown in fig. S5.) Process I with thick Ni film left zigzag corrugation on the surface of the released layer and the substrate because the layer release occurred in the bulk. On the other hand, the SEM images show that the surfaces of the released layers after processes II and III were flat, and the images indicate that the layer release occurred, respectively, at the target InP/InGaAs junctions because the thicknesses of the epitaxial layers in the released layers and remaining structures were the same as the junction depths of the heterostructure. In the SEM images, the color and brightness of the relatively thin epitaxial layers have been adjusted to make them more visible (see fig. S6 for the original SEM images). From the surface images taken after the spalling, we could also estimate the yield of the layer release at the heteroepitaxial interface. The estimated yield was about 78% (see fig. S7 and note S5 for details of the yield estimation). In addition, we could evaluate the thickness uniformity by measuring the released surface morphology after processes II and III over the entire region of the spalled sample (sample size of 15 × 15 mm2). The results indicate that both processes II and III enabled uniform layer release at the target heteroepitaxial interfaces (i.e., local symmetry planes we designed) in the large area of the sample (>12 × 12 mm2) except for the sample edge regions (figs. S8 and S9).

Characterizations of the layer-resolved mechanical separation technique

We investigated the elemental compositions and structural information of the layers to confirm that layer release occurred at the target junctions between the InGaAs and InP epitaxial layers (Fig. 3). Cross-sectional SEM images and EDS elemental-mapping images (P, In, Ga, and As) of the released epitaxial layers and the remaining substrates are shown in Fig. 3 (A and B) for processes II and III, respectively. Because process II was designed to separate the interface between n-InP and n-InGaAs, the released structure was composed of three epitaxial layers (InP/InGaAs/InP), as could be observed from the SEM image. The elemental-mapping image of the released layer is clearly divided into three different regions. As shown in Fig. 3A, the Ga and As composition signals are depleted in the top and bottom regions, and the P signal is depleted in the middle region of the released layer while the P composition signal is depleted in the thin top region of the remaining substrate. In the case of process III, the released layer is composed of two epitaxial layers (InP/InGaAs), and the remaining substrate has two epitaxial layers on the InP bulk. This compositional structure can be also confirmed by elemental-mapping images for process III (Fig. 3B). The P signal is depleted in the bottom region of the released layer, while the Ga and As signals are depleted in the top of the remaining substrate. For more rigorous confirmation, we analyzed the III-V structure of the released layers and the remaining substrates by measuring Raman spectroscopy on their surfaces after layer release by processes II and III. Figure 3C shows the Raman spectra for process II. The two primary peaks of the Raman spectrum measured on the surface of the released layer correspond to the InP-like longitudinal optical (LO) mode and transverse optical (TO) mode (). The main peaks observed on the surface of the remaining substrate correspond to the InAs-like LO mode and the GaAs-like LO mode (, ). On the other hand, the Raman spectra for process III indicate that the main peaks on the released layer correspond to the InAs-like LO mode and the GaAs-like LO mode, and those on the substrate correspond to the InP-like LO and TO modes (Fig. 3D). These results clearly confirm that spalling process II released the InP/InGaAs/InP epitaxial layer and process III released the InP/InGaAs epitaxial layer. The important aspect of these results is that the proposed process can enable a III-V spalling technique that can selectively release single-crystalline epitaxial layers of interest from a III-V heterostructure wafer by controlling the strain energy induced by the Ni film. Last, to confirm the presence of an intermixing layer that plays a dominant role in enabling the flat and uniform layer release at the target epitaxial interfaces, we performed transmission electron microscopy (TEM) and additional Raman analysis on the interface between InP and InGaAs layers. High-resolution TEM images and the additional Raman investigation showed the lattice-matched InP/InGaAs heterostructure contains an intermixing layer with a two- or three-monolayer thickness at the epitaxial interface between InP and InGaAs layers (fig. S10).

Fig. 3.

Confirmation of layer-resolved release of epitaxial layers at different InP/InGaAs junctions.

(A and B) Cross-sectional SEM images and EDS elemental-mapping images of the released layer and the remaining substrate after (A) process II and (B) process III. Scale bars, 1 μm. The spatial distributions of the P, In, Ga, and As signals of EDS agree well with the elements of each epitaxial layer. The dashed lines indicate the interfaces between the heteroepitaxial layers determined from the SEM images. (C and D) The Raman spectra measured from the surface of the released layer (red arrows in the insets) and the remaining substrate (blue arrows in the insets) after (C) process II and (D) process III. The spectra with the InP-like LO and TO mode peaks indicate InP surfaces, and those with the InAs-like LO mode and GaAs-like LO mode peaks correspond to InGaAs surfaces. This result shows that the epitaxial layers are precisely released at the different target InP/InGaAs junctions of the heterostructure via processes II and III. a.u., arbitrary units.

To confirm whether the proposed layer-release technique can be applied to practical applications, we transferred the released layer onto a Si(100) substrate and investigated the crystal and material qualities of the transferred epitaxial layers (Fig. 4). The transfer process was performed by a spin-on-glass process with a tetraethyl orthosilicate (TEOS)–based SiOx-bonding layer (, ). Because the surface of the layer released by the proposed technique was flat, we could reliably transfer the epitaxial layer (InP/InGaAs) onto the Si substrate without any air voids at the interface between the epitaxial layer and bonding layer (Fig. 4A). We characterized the surface morphology of the released layers by using AFM measurement. As shown in Fig. 4B, the surface of the released layer was atomically flat with a root-mean-squared surface roughness of ~3.7 Å. This flatness is comparable with the spalling result of elemental semiconductors (). Figure 4C shows the characterization on the crystallinity of the transferred epitaxial layer based on the high-resolution XRD measurement. The slight shift in XRD peaks toward higher diffraction angles (~0.005°) indicates that there was a weak remaining compressive stress after the transfer, and the full-width at half-maximum values less than 0.01° (<40 arc sec) of the XRD peaks corresponding to the (004) lattice of transferred InGaAs and InP indicate that there was no noticeable degradation in crystal quality of the single-crystalline epitaxial layer after the processes. In addition, we confirmed the material quality of the transferred epitaxial layer by measuring the steady-state PL characteristics at room temperature. There was no noticeable difference between the spectrum of the epitaxial layer as-grown on InP and that of the released/transferred layer (Fig. 4D). No peak shift induced by the optical-bandgap change nor peaks activated by defects were observed after the processes. Consequently, these structural and optical characterization results indicate that the proposed layer-resolved mechanical separation process enables atomically flat release and transfer of a III-V(100) epitaxial layer without noticeable degradation in both crystal and material quality.

Fig. 4.

Characterization of InP/InGaAs epitaxial layer transferred onto an Si substrate.

(A) Cross-sectional SEM image of the transferred InP/InGaAs epitaxial layer on an Si(100) substrate after process III and (B) an AFM image of the surface of the released epitaxial layer (root-mean-squared surface roughness of 3.7 Å), showing that the surface of the released layer is atomically flat and the layer can be transferred without air voids. (C) High-resolution XRD ω–2θ scans of the InP/InGaAs epitaxial layer grown on the InP substrate and transferred onto the Si substrate, showing XRD peaks corresponding to the (004) lattice of InGaAs and InP (inset, wide-range XRD ω–2θ scan including the Si lattice). (D) Steady-state room temperature PL spectra of the InP/InGaAs epitaxial layer grown on the InP substrate and transferred onto the Si substrate. These results indicate that the layer-resolved mechanical separation process enables atomically flat release and transfer of a III-V epitaxial layer without degradation in both crystal and material quality.

DISCUSSION

In summary, we proposed a layer-resolved mechanical separation technique that can selectively release III-V(100) epitaxial layers of interest from a normal lattice-matched heterostructure without an embedded sacrificial buffer. Because the layer release precisely occurs at a heteroepitaxial interface with a relatively weak surface energy, this technique can enable atomically flat and uniform release of single-crystalline III-V epitaxial layers without degradation in crystal and material quality. Furthermore, we demonstrated that the target heteroepitaxial interface for layer release can be selectively determined by controlling the strain energy induced by the Ni stressor film. This technique will offer an effective processing technique required for heterogeneous integration of III-V compound semiconductors with Si or other substrates and provide high fabrication flexibility in compound semiconductor technology.

MATERIALS AND METHODS

Epitaxial growth

The InP/InGaAs heterostructure was epitaxially grown on a 2-inch on-axis n-InP(100) wafer by a MOCVD reactor (D180 LDM, Veeco Inc.). After growing a 0.3-μm-thick buffer layer (Si-doped n-InP) on the InP substrate, a lattice-matched 0.2-μm-thick n-In0.53Ga0.47As layer (Si doped with a doping concentration of 5 × 1016 cm−3) was grown as an etch-stop layer for n-type contact formation. For a p–i–n structure, a 1-μm-thick n-type contact layer (Si-doped InP), 2.8-μm-thick active layer (undoped In0.53Ga0.47As), and 0.5-μm-thick p-type contact layer (Zn-doped InP) were sequentially grown. The doping concentrations of the n-InP and p-InP contact layers were 3 × 1018 and 5 × 1017 cm−3, respectively. In this growth process, the InP/InGaAs epitaxial layers were grown at 650°C under N2 ambience, and phosphine, trimethylindium, trimethylgallium, and arsine were used as P, In, Ga, and As precursors, respectively.

Mechanical release of thin semiconductor layers

The Si, GaAs, InP, and InP/InGaAs heteroepitaxial layers were mechanically released by the Ni stressor film with a handling layer. Before the deposition of the Ni film, a 20-nm-thick Ti film was deposited by DC magnetron sputtering with a system power of 600 W and a working pressure of 3 mT to promote adhesion between the Ni film and substrate. Subsequently, in the same chamber, an Ni film with a high internal tensile stress was deposited with a system power of 300 W and a working pressure of 3 mT. After unloading the Ni-deposited samples and cooling them to room temperature, the semiconductor layers were released from their substrates by using a thermal-release tape (Revalpha, Nitto Denko Inc.) as a handling layer for the layer release/transfer process. In this step, we attached the thermal-release tape on top of the Ni film and manually applied an external lifting force to the sample using the handling tape to initiate the crack at the sample edge. After the crack initiation, because of the high stress induced by the Ni film, the crack propagated almost spontaneously until the semiconductor layer was completely released from the substrate.

Transfer of released semiconductor layers

The released semiconductor layers were transferred onto an Si substrate by using the spin-on-glass process (, ). First, TEOS-based solution-processable SiOx was spin coated on the Si substrate as a bonding layer; then, a released semiconductor layer was placed onto the SiOx-coated Si substrate. Subsequently, to cure the SiOx layer and bond the semiconductor layer with the Si substrate, we baked the sample at 120°C for 2 hours with applying a pressure of 55 g cm−2. In this step, the thermal release tape was detached from the surface of the sample because of the baking temperature being higher than the release temperature of the tape (90° to 120°C). The thickness of the SiOx layer was about 500 nm after the baking step. Last, the stressor film was completely removed by wet etching. The Ni film was etched in a 0.1 M ferric chloride (FeCl3) solution, and the thin Ti layer was etched in a diluted (1%) hydrogen fluoride solution.

Stress measurement

The internal stress of the Ni film was measured with a multibeam optical sensor system (). In this measurement, the internal stress was estimated on the basis of Stoney’s method (), which is a standard method for measuring film stress. The internal stress was deduced from the curvature change in the film/substrate, which was estimated from the change in the measured spacing between multiple beams. The relation between the internal stress of the film and the measured beam spacing is given bywhere σf, Δd, d0, Ys, vs, ts, tf, α, and L are the internal stress of film, the difference in beam spacing due to stress-induced curvature, the initial beam spacing before film deposition, the Young’s modulus of the substrate, the Poisson ratio of the substrate, the thickness of the substrate, the thickness of the film, the detection angle, and the detection length, respectively. To calculate the estimated spalling depth as a function of Ni thickness, we deposited Ni films with various thicknesses on InP(100) substrates and measured the internal stresses depending on their thicknesses.

Characterizations

The cross-sectional images of the released layers and the remaining substrates and the mapping images of their elemental compositions were obtained by using field-emission SEM (SU8220, Hitachi Inc.) combining with EDS (MX80, Oxford Instruments Inc.). The III-V structures on the surfaces of the released layers and the remaining substrates were evaluated via Raman spectroscopic measurement (inVia reflex, Renishaw Inc.) with a laser wavelength of 532 nm. The AFM image was obtained by the tapping-mode operation of a scanning probe microscope (NX20, Park Systems Inc.). An AC-mode Si probe with a resonance frequency of 300 kHz was used for imaging. The crystal quality of the epitaxial layers was characterized by an XRD measurement system (Empyrean, Malvern PANalytical Inc.) with Cu Kα radiation operated at 40 kV and 25 mA. The material quality was characterized by a PL measurement system (LabRAM HR-800, Horiba Jobin Yvon Inc.) with a 514-nm line laser and a Ge photodetector. The cross-sectional images of the heteroepitaxial interface between the InP and InGaAs layers were obtained by using field-emission TEM (Titan G2 ChemiSTEM Cs Probe, FEI Company Inc.).