Can Carbon Nanotube Transistors Be Scaled Down to the Sub-5 nm Gate Length?

Single-walled carbon nanotubes (CNTs) have been considered as a promising semiconductor to construct transistors and integrated circuits in the future owing to their ultrathin channel thickness and ultrahigh injection velocity. Although a 5 nm gate-length CNT field-effect transistor (FET) has already been experimentally fabricated and demonstrates excellent device performance, the potential or constraint factors on performance have not been explored or revealed. Based on the benchmark of the device performance between the experimental and simulated 5 nm gate-length CNT FETs, we use the first-principles quantum transport approach to explore the performance limit of CNT FETs based on the gate-all-around (GAA) device geometry for the first time. It is found that the GAA CNT FETs can fulfill the ITRS 2028 high-performance target in the 2 nm gate-length node in terms of the on-state current, delay time, and power consumption. We also find that the energy-delay product of the CNT FETs is superior to those of the high-performance 2D materials and Si Fin FETs at the sub-5 nm gate length due to its unique electrical property. Though theoretically the gate length of CNT FETs can be potentially scaled to 2 nm, considering the tradeoff between the performance and power consumption, 5 nm is the ultimate scaled limit.