| Literature DB >> 33842011 |
M E Fouda1,2, A M AbdelAty3, A S Elwakil4,5,6, A G Radwan1,6, A M Eltawil2,7.
Abstract
INTRODUCTION: Constant Phase Elements (CPEs) have been widely used in many applications due to the extra degree of freedom, which offers new responses and behaviors.Entities:
Keywords: Approximation; CPE; Crossbar array; Flower pollination algorithm; Fractional-order capacitor; Memristor
Year: 2020 PMID: 33842011 PMCID: PMC8020297 DOI: 10.1016/j.jare.2020.08.007
Source DB: PubMed Journal: J Adv Res ISSN: 2090-1224 Impact factor: 10.479
Fig. 2(a) 3D crossbar array containing RRAMs (i.e., memristors), (b) resistive network of the crossbar array with general impedance loading, and (c) simplified model of the array for CPE approximation.
Fig. 1Alternative approaches and different methods for approximating a CPE [9], [13], [14], [15], [16], [17], [18], [19], [21], [22], [23], [25], [26], [27], [28], [29], [30], [31], [32], [33], [34], [35].
Optimal parameters values for selected fractional orders. The mean and coefficient of variation (COV) are summarized for 54 independent runs where .
| Mean | COV | Mean | COV | Mean | COV | Mean | COV | |
|---|---|---|---|---|---|---|---|---|
| Fmin | ||||||||
Fig. 3(a) Phase error in degrees and (b) pseudo-capacitance percentage tolerance. (c) and (d) 200 Monte-Carlo simulations with tolerance of phase and pseudo-capacitance, respectively. (e) and (f) Maximum relative phase error versus different number of branches for approximation using (3) and parallel RC approximation using (4), respectively.
Circuit parameters values generated using the Valsa algorithm where .
| 810 |
Optimal circuit parameters values for the proposed topology with no .
Percentage capacitance and phase errors comparison between the proposed approach, Valsa [21], and sum of high-pass filters (Xbar w/o ) [25].
Fig. 4(a) Fractional-order relaxation oscillator circuit schematic and (b) obtained oscillation on the left y-axis and relative error percentage on right y-axis with changing . Subplots show the transient simulation of the output voltage and the CPE voltage .
Fig. 5(a) Phase relative error for different fractional-orders with same capacitive loading with .
Fig. 6(a) Equivalent circuit schematic of separate multiple CPEs design. (b) and (c) Relative phase error for different fractional-orders sharing the same capacitive loading with .
Convergence curves for 3 investigated designs.