| Literature DB >> 33758215 |
Goutham Arutchelvan1,2, Quentin Smets3, Devin Verreck3, Zubair Ahmed3, Abhinav Gaur4, Surajit Sutar3, Julien Jussot3, Benjamin Groven3, Marc Heyns3,4, Dennis Lin3, Inge Asselberghs3, Iuliana Radu3.
Abstract
Two-dimensional semiconducting materials are considered as ideal candidates for ultimate device scaling. However, a systematic study on the performance and variability impact of scaling the different device dimensions is still lacking. Here we investigate the scaling behavior across 1300 devices fabricated on large-area grown MoS2 material with channel length down to 30 nm, contact length down to 13 nm and capacitive effective oxide thickness (CET) down to 1.9 nm. These devices show best-in-class performance with transconductance of 185 μS/μm and a minimum subthreshold swing (SS) of 86 mV/dec. We find that scaling the top-contact length has no impact on the contact resistance and electrostatics of three monolayers MoS2 transistors, because edge injection is dominant. Further, we identify that SS degradation occurs at short channel length and can be mitigated by reducing the CET and lowering the Schottky barrier height. Finally, using a power performance area (PPA) analysis, we present a roadmap of material improvements to make 2D devices competitive with silicon gate-all-around devices.Entities:
Year: 2021 PMID: 33758215 DOI: 10.1038/s41598-021-85968-y
Source DB: PubMed Journal: Sci Rep ISSN: 2045-2322 Impact factor: 4.379