| Literature DB >> 33719412 |
Yiru Wang1, Limin Kang1, Zhenliang Liu1, Zuteng Wan1, Jiang Yin1, Xu Gao2, Yidong Xia1, Zhiguo Liu1.
Abstract
Organic field-effect transistors (OFETs) as nonvolatile memory units are essential for lightweight and flexible electronics, yet the practical application remains a great challenge. The positively charged defects in pentacene film at the interface between pentacene and polymer caused by environmental conditions, as revealed by theoretical and experimental research works, result in unacceptable high programming/erasing (P/E) gate voltages in pentacene OFETs with polymer charge-trapping dielectric. Here, we report a pentacene OFET in which an n-type semiconductor layer was intercalated between a polymer and a blocking insulator. In this structure, the hole barrier caused by the defect layer can be adjusted by the thickness and charge-carrier density of the n-type semiconductor interlayer based on the electrostatic induction theory. This idea was implemented in an OFET structure Cu/pentacene/poly(2-vinyl naphthalene) (PVN)/ZnO/SiO2/Si(p+), which shows low P/E gate voltages, large field-effect mobility (0.73 cm2 V-1 s-1), fast P/E speeds (responding to a pulse width of 5 × 10-4 s), and long retention time in air.Entities:
Keywords: field-effect transistor; hole barrier; memory; n-type semiconductor; pentacene
Year: 2021 PMID: 33719412 DOI: 10.1021/acsami.0c19603
Source DB: PubMed Journal: ACS Appl Mater Interfaces ISSN: 1944-8244 Impact factor: 9.229