| Literature DB >> 33572563 |
Gwan Beom Hwang1, Kwon Neung Cho1, Chang Yeop Han1, Hyun Woo Oh1, Young Hyun Yoon1, Seung Eun Lee1.
Abstract
The development of the mobile industry brings about the demand for high-performance embedded systems in order to meet the requirement of user-centered application. Because of the limitation of memory resource, employing compressed data is efficient for an embedded system. However, the workload for data decompression causes an extreme bottleneck to the embedded processor. One of the ways to alleviate the bottleneck is to integrate a hardware accelerator along with the processor, constructing a system-on-chip (SoC) for the embedded system. In this paper, we propose a lossless decompression accelerator for an embedded processor, which supports LZ77 decompression and static Huffman decoding for an inflate algorithm. The accelerator is implemented on a field programmable gate array (FPGA) to verify the functional suitability and fabricated in a Samsung 65 nm complementary metal oxide semiconductor (CMOS) process. The performance of the accelerator is evaluated by the Canterbury corpus benchmark and achieved throughput up to 20.7 MB/s at 50 MHz system clock frequency.Entities:
Keywords: embedded processor; graphical user interface; hardware accelerator; inflate algorithm; lossless compression; system-on-chip
Year: 2021 PMID: 33572563 PMCID: PMC7911039 DOI: 10.3390/mi12020145
Source DB: PubMed Journal: Micromachines (Basel) ISSN: 2072-666X Impact factor: 2.891