Reduction of charge offset drift using plasma oxidized aluminum in SETs.

Aluminum oxide ([Formula: see text])-based single-electron transistors (SETs) fabricated in ultra-high vacuum (UHV) chambers using in situ plasma oxidation show excellent stabilities over more than a week, enabling applications as tunnel barriers, capacitor dielectrics or gate insulators in close proximity to qubit devices. Historically, [Formula: see text]-based SETs exhibit time instabilities due to charge defect rearrangements and defects in [Formula: see text] often dominate the loss mechanisms in superconducting quantum computation. To characterize the charge offset stability of our [Formula: see text]-based devices, we fabricate SETs with sub-1 e charge sensitivity and utilize charge offset drift measurements (measuring voltage shifts in the SET control curve). The charge offset drift ([Formula: see text]) measured from the plasma oxidized [Formula: see text] SETs in this work is remarkably reduced (best [Formula: see text] over [Formula: see text] days and no observation of [Formula: see text] exceeding [Formula: see text]), compared to the results of conventionally fabricated [Formula: see text] tunnel barriers in previous studies (best [Formula: see text] over [Formula: see text] days and most [Formula: see text] within one day). We attribute this improvement primarily to using plasma oxidation, which forms the tunnel barrier with fewer two-level system (TLS) defects, and secondarily to fabricating the devices entirely within a UHV system.

Introduction

The future of large scale quantum computing depends on successfully merging diverse materials and qubit architectures that each realize different functionalities, i.e., computation, cache, memory or long range transmission. To accomplish this, quantum information must be efficiently transduced between bases, e.g. superconducting and semiconducting qubits, requiring mutually compatible materials and designs. Specifically within those two realms, aluminum and its native oxides () have enabled great advances, providing simple and reliable tunnel couplings in superconducting circuits[1-3] and isolation oxides between nanoscale gates for semiconducting qubit control[4,5]. However, superconducting qubits still suffer from unacceptably high relaxation rates, motivating device designs that minimize utilization and the electric field density within the oxides (reduced participation factor). Similarly, aluminum implementation in semiconducting devices is most successful the farther the aluminum is from the sensitive region of the device[4,6-8]. In both cases, the amorphous formed during thermal oxidation is thought to have a high density of electrically active defects originating from its nonequilibrium structure[9,10], which interact with the quantum system and create a substantial loss mechanism.

None-the-less, aluminum and remain highly desirable choices due to the nearly ideal WKB-like (Wentzel–Kramers–Brillouin) attenuation of states in the tunnel barriers, i.e., minimal tunneling dependence on angular momentum, spin, etc., and their compatibility with nanofabrication techniques. Therefore, efforts to identify and suppress the instabilities of are of great significance for enhancing qubit performance. Further, establishing stable aluminum oxides enables expanded use of metal single-electron transistors (SETs), like those used in this study, to be used as surface mounted charge sensors, reducing the density of in-plane circuit elements. These charge sensors could, for example, provide projective spin readout through spin-to-charge conversion techniques already demonstrated[8,11,12].

SETs are considered to be the world’s most sensitive electrometers, with the capability of detecting the motion of individual electrons or charge instabilities[13-17]. The same sensitivity that enables exquisite readout of a target qubit is also susceptible to any other charge motion within the local environment, e.g., unintentional charge defects. In this study, we use that sensitivity as a probe of whether sufficiently stable charge environments can be realized.

Ideally, the dependence of the SET’s source-drain current on the gate voltage (control curve) will have a periodic behavior with each period corresponding to a 1 e change in the island’s net charge. When the source-drain bias , this will look like a series of sharp peaks, but at modest bias (temperature), i.e., , the function smooths out similar to a sinusoid, where is the island charging energy, is the Boltzmann constant, e is the elementary charge and is the effective electron temperature. Changes in the control curve’s phase indicate uncontrolled changes in the SET’s local electrostatic environment. The time trace of the phase is a sensitive indicator of stability and phase changes are known as charge offset drift, denoted by .

Extensive prior work examining the charge offset stability of various materials showed that metallic SETs incorporating tunnel barriers demonstrate severe time instability—random, time-dependent phase fluctuations in the control curve[13-18]. These large, abrupt changes are attributed to two-level system (TLS) defects associated with amorphous , consistent with similar findings from TLS spectroscopy studies in the context of superconducting qubits[19-21]. In our prior work, we mitigated long-term, macroscopic resistance drift using plasma oxidized tunnel barrier devices[22], a behavior thought to originate from the same bath of defects that causes significant charge offset drift[23,24]. Plasma oxidation, compared to conventional thermal oxidation, incorporates higher oxygen content in the barrier layer at a considerably faster rate, resulting in a much better initial quality[25-27]. To explore whether the macroscopic improvements seen in plasma oxidized improve the feasibility for use in quantum computing applications, we fabricated metallic SETs with plasma oxidized tunnel barriers and measured their long-term charge offset drift. We find these devices exhibit significantly reduced charge offset drift—the best over days and no observation of exceeding , compared with any other previously reported metallic SETs[13,17,18,28] where the best over days and most within one day. Uncertainties presented in this paper represent standard deviations (SDs) unless otherwise stated. We attribute this improvement to (i) using plasma oxidation to form the tunnel barriers and (ii) fabricating the devices entirely within a system of ultra-high vacuum (UHV) chambers.

Results

Device design and characterization

The device fine structures are fabricated via double-angle, shadow evaporation[29] in a system of UHV chambers with a base pressure of equipped with deposition and plasma oxidation capability (see Ref.[22] for equipment details). Figure 1a shows a scanning electron microscope (SEM) image of the device fine structure with a schematic cross-section through the tunnel junction in Fig. 1b. The blue part is the bottom layer—2 nm cobalt (sticking layer) with 20 nm aluminum deposited at a first angle on the thermally oxidized silicon substrate. The wafer is then transferred to the plasma chamber where the surface of the bottom layer is oxidized using a DC plasma at 21 Pa (160 mTorr) of research grade oxygen with 57 W to 60 W for 7 s. The oxide is then allowed to relax in vacuum for at least 12 h before the top layer is deposited, consistent with prior work[22] mitigating resistance drift. The layer produced under this condition is estimated thick[22]. Note that although plasma can attack the electron-beam (e-beam) resist used for shadow evaporation, the influence of oxygen plasma on the e-beam pattern at this step is negligible since the resist has been coated by the metal in the first deposition. The wafer is then transferred back to the deposition chamber where 30 nm aluminum is deposited at a second angle for the top layer, as shown in green in Fig. 1a. By controlling the deposition angle, the size of the island and tunnel junctions can be controlled to a precision of along the direction of rotation. Additionally, the pattern is designed so that, depending on angle, some features do not appear in both layers. During the deposition steps, a liquid nitrogen cryoshroud is kept cold to insure high vacuum. The substrate temperature begins at ambient temperature and is expected to warm somewhat.

Figure 1

(a) False-colored SEM image of an SET identical to the one discussed in this paper. The blue part is the bottom layer with plasma oxide on the surface and the green is the top layer. (b) A cross-sectional cartoon through the tunnel junction of the SETs.

When a metallic island is separated from source and drain reservoirs by tunnel junctions, the resulting SET can confine an integer number of electrons on the island. As a result of this charge quantization, the charging energy required to add or remove a single electron from the island is , where is the island’s total capacitance. Coulomb blockade due to discrete electron charges is strongly visible when: i) the tunnel junction conductances (h is the Planck constant), and ii) [30]. If the bias , then the spacing between single electron energy levels is larger than the bias window and for some values of no energy levels on the island will fall within the bias window. In that case, the source-drain current can be , known as Coulomb blockade. When a single electron energy level on the island does fall within the source-drain bias window, then electrons can tunnel on and off of the island, producing a source-drain current . The maximum of is reached when an energy level is fully within the bias window, producing a conductance peak that may be broadened by bias or temperature. As is swept, different energy levels move through the bias window, producing a periodic current oscillation vs. , referred to as Coulomb blockade oscillation (CBO). The oscillation period is determined by the capacitance between the gate and the island, . Since the total charge on the metallic island is , is approximately constant and the charging energy is assumed constant. When the temperature or bias becomes significant compared to the charging energy, these peaks merge into oscillations that are nearly sinusoidal.

To conduct the charge offset drift measurements, the samples are cooled in a cryogen-free dilution refrigerator (DR) with a base temperature of approximately . As shown in Fig. 1a, the SET consists of a small conducting island coupled to the source and drain electrodes through two tunnel junctions. The gate electrode is capacitively coupled to the island and manipulates the electrostatic potential via the gate voltage , modifying the charge configuration of the island. A small, constant DC bias, , is applied on the drain electrode while measuring the current via a transimpedance amplifier on the source electrode, . On the time scale of seconds, the standard deviation/typical noise of the current and voltage are and , respectively. The device’s control curve is observed by measuring vs. applied on the gate electrode. A typical charge offset drift measurement involves repeatedly measuring this control curve every few minutes for about one week, as discussed further below.

The devices used in this study and shown in Fig. 1 are designed to exhibit Coulomb blockade behavior at temperatures K. Based on the lithographic design and SEM images of similar devices, we estimate the single tunnel junction dimensions are () nm by () nm. Using a parallel plate capacitor model with an permittivity of and a thickness of () nm, we estimate each junction capacitance to be () aF ( is the vacuum permittivity). A gate capacitance of () aF was calculated by modelling a gate of () nm () nm () nm (length width height) and an island of () nm () nm () nm with a separation of () nm on a /Si substrate using the capacitance solver FastCap and a permittivity[31] of . Therefore, a CBO period of () mV is expected on these devices. Adding up these capacitance gives an expected charging energy, .

Charge offset drift measurement

In prior studies of SETs, the local electrostatic environment of the island would often change with time randomly, which appears as the phase of the CBO fluctuating with time. This time instability, referred to as charge offset drift, has been an issue in metallic SET devices for a long time. Many factors contribute to the vulnerable electrostatic environment of the island, including unintentional charge defects from multiple fabrication processes, temporal or thermal material relaxation, circuit noise, etc.

Figure 2a illustrates an example CBO from an SET (W119-C1) at the base temperature of , with oscillations from each single electron conductance peak moving through the bias window as is swept. In this case, the bias voltage is applied on the drain electrode, with the current measured on the source, and the current oscillates sinusoidally. The nonideal broadening is believed to be due to a noise-induced high , which prevents complete Coulomb blockade, discussed further below. The nonzero current offset observed in the CBO is attributed partially to the merged peaks and an imperfect zero on the current preamplifier. For this device, the oscillation period , from which the gate capacitance aF, is in agreement with the design estimate of () aF.

Figure 2

(a) A representative vs. CBO from an SET (W119-C1) at with an applied bias taken from d in panel (b), a color map of vs. spanning week. The vertical stripes indicate that the CBO phase remains stable with time. For this device, , from which we find a gate capacitance aF. (c) The charge offset, , extracted from the phase in (b), as a function of the time. A linear drift of is observed, with one small jump exists from to . The total charge offset drift over days is .

To evaluate the charge offset stability in our plasma oxidized SETs, the CBO is repeatedly measured every five minutes over many days for device W119-C1. The result of this long-term repetitive measurement is shown in Fig. 2b. For each sweep, the value on the y-axis is the time when that sweep ends. The color scale on the z-axis represents the value measured from the source electrode. The high and low current values form vertical stripes in time, which clearly show that the CBO phase in our SET remains quite stable without sudden shifts over the course of more than 7 days. Compared to the results from Al SET devices with thermally oxidized tunnel barriers[13,17,18,28], this device exhibits much improved charge offset stability.

To numerically evaluate the stability, we extract the charge offset, , from the repeated sweeps. Here we use two methods for the data compared in this paper and the two methods are consistent within 10 %, verified by Hu et al.[32] If the source-drain current oscillates nearly sinusoidally as a function of the gate voltage, the measured vs. is fit to:where is the oscillation amplitude, is the phase for a given t and is a nonideal offset. For each line in Fig. 2b, the measured current data is fit to Eq. 1. Then the charge offset as a function of each sweep, as a set of , is plotted as a function of time in Fig. 2c. These data do not exhibit the dramatic, abrupt jumps characteristic seen in devices of prior work (one small jump exists from to ), but do show a slow, linear drift of . The total charge offset drift over days is , where is defined as the full range of values measured and the uncertainty is calculated as the standard deviation of 100 data points in a stable range. For previously reported metallic SETs with thermally oxidized tunnel junctions, most are much greater than and show many abrupt jumps[13,17,18,28].

When the SET control curve displays sharper peaks and cannot be well fit sinusoidally, individual peaks of the CBO are fit to a Gaussian to locate the peak’s center position:Here, , and denote the area/height parameter, center position and full width at half maximum (FWHM) of each Gaussian peak, respectively. In this case, , where is the gate voltage difference between two adjacent peaks. Data from another device (W119-C3) is shown in the supplementary information where is calculated in this way. That device shows one abrupt jump of after d of measurement, but is otherwise stable with a linear drift of . In that device, we find the over days is () e. A summary of results from three plasma oxidized devices fabricated in this work, three thermally oxidized devices presented in Ref.[18], and the best known result from an all-silicon device with no metals published in Ref.[33], which is thought to have less TLS defects than devices containing , are shown in Table 1. The measurement duration ‘’, ‘jumps’ and from the longest single cooldown of each device are calculated and compared. The uncertainty of in each device (not relevant on the two devices drifting more than 1 e) is defined as the standard deviation of 100 data points in one stable range, which indicates the measurement stability. For devices fabricated in this work, W119-C3 has the same device geometry as W119-C1 (the one discussed above), while W119-T1-2 has an alternative “in-line” geometry (shown in the supplementary information), but all of them exhibit extended periods ( days) without jumps. Note that the charge offset drift measurements of W119-T1-2 were often interrupted and stressed by other measurements (see supplementary information for details). This device correspondingly exhibits jumps after measurement breaks and larger uncertainty, but the charge offset stability in each continuous interval remains stable. As summarized in Table 1, all our plasma oxidized devices are much more stable than the historic thermally oxidized ‘NIST-G’ and ‘NIST-B’ devices in Ref.[18], while they are comparable to the ‘PTB’ device, which is thought to be the best metallic device in Ref.[18]. The nonmetallic, silicon SOI (silicon-on-insulator) device from Ref.[33] is included for reference as one of the best results from an extended charge offset stability measurement. We systematically find our metallic devices are much more stable, with no evidence in any measurements of the gross, erratic charge offset seen in the historic metallic devices.

Table 1

Comparison of charge offset stabilities for several devices used in this study and available in the literature, with a silicon SOI device as a high quality benchmark in the last row.

Device	t_meas (d)	Jumps	ΔQ_0 (e)
W119-C1	7.6	1	0.13±0.011
W119-C3	7.6	1	0.30±0.014
W119-T1-2	3.9	2a	0.68±0.038
NIST-G (Ref.[18]—Fig. 3)	18.8	> 100b	≥1
PTB (Ref.[18]—Fig. 4)	9.0	7c	0.43±0.007
NIST-B (Ref.[18]—Fig. 5)	7.5	> 50b	≥1
SOI Si (Ref.[33]—Fig. 7)	7.9	0	0.03±0.003

W119-C1 charge offset drift data are shown in the main text, other new data presented in this study are in the supplementary information. is the total span of charge offset drift data, which includes break in some cases, a ‘jump’ occurs when the 100 pt running standard deviation increases by a factor of three, ‘’ is defined as the full range of the values measured.

aNon-contiguous measurements with multi-hour breaks;bMain method doesn’t apply and number of jumps is roughly estimated by times of change .c5 out of 7 jumps are correlated with liquid helium transfers.

Temperature dependence measurement

Finally, we use the temperature dependence of the current lineshape to determine the total capacitance and charging energy for two devices in comparison with the design values. The absence of strong Coulomb blockade in W119-C1, as shown in Fig. 2, prevents estimation of and using a Coulomb diamond measurement. As mentioned earlier, strong Coulomb blockade behavior can only be observed when . As the bath temperature increases, the source/drain reservoirs broaden and the single electron conductance peaks will be thermally broadened[34]. An individual current peak in this regime is described as[30,34,35]:where is the reference current characterized by the bias voltage, the device resistance outside of blockade (), and is the lever arm. Therefore, as the bath temperature (T) increases from the base temperature ( mK), the current peaks spaced by thermally broaden and eventually blend together. Experimentally, the CBO is typically only visible when [30]. Figure 3a shows CBO sweeps as a function of the temperature from W119-C1. As expected, the oscillations die down with increasing temperature and vanish at temperatures above K, when the oscillation is lost in the noise. The blue solid line at the bottom in Fig. 3a shows the model CBO curve calculated from an array of 25 current peaks (Eq. 3) that span spaced by based on the extracted and values as listed above, , (taken from separate vs. measurements) and adjusted to match the temperature dependence below. Note that it is important to include sufficient number of peaks outside the window to capture tails of peaks. The peak-to-peak amplitude of the CBO vs. temperature is shown in Fig. 3b where the red squares (blue diamonds) are from W119-C1 (W119-C3) in Fig. 3a (Fig. S1d in supplementary information). The red (blue) dotted line shows the peak-to-peak amplitudes taken from model curves like that shown in Fig. 3a, where aF (329 aF) is adjusted to best capture the experimental trend while using all other experimentally determined quantities. The blue shaded region around the blue dotted line shows the peak-to-peak amplitude range for W119-C3 corresponding to varying over a range of , centered around the best-fit value, where . The experimental values and the model values agree well at temperatures . The discrepancy at temperatures below 0.75 K implies that the electron temperature for W119-C1 is around . The gray shaded region at the bottom indicates the limit given by the current noise. The oscillations are not visible when the temperature is , which also agrees with Ref.[30] that oscillations are not visible when . The good agreements between the lines and the data allow us to constrain the uncertainty of to within about and the best-fit values agree well with the design values for these devices given above. Taken as a whole, these measurements indicate the devices were realized as designed and are functioning in the single electron regime consistent with the accepted theory.

Figure 3

(a) CBO on the SET (W119-C1) at varying temperatures. As expected, the oscillations die down with increasing temperature and vanish for when the oscillations drops below the noise—gray shaded region in (b). The blue solid line at the bottom represents the model CBO curve at 0.75 K as discussed in the main text. (b) The symbols show CBO peak-to-peak amplitudes extracted from the oscillations like those in (a) vs. temperature. Red squares (blue diamonds) are extracted from W119-C1 in (a) (W119-C3 in Fig. S1d of the supplementary information). The two data points near 2 K are found by fitting a sine function to the CBO to suppress noise and the fitting errors are represented by the vertical error bars. All other data points are peak-to-peak amplitudes found by the average of adjacent peak-to-valley values from the CBO and the vertical error bars represent the standard deviation of all peak-to-valley values at that temperature. The horizontal error bars represent temperature fluctuations within min of the log time. Temperature errors are not shown. The red (blue) dotted line represents the peak-to-peak trend from the model when for . The blue shaded region shows the model variation when varies such that varies over a range of , centered around the best-fit value. The gray shaded region at the bottom indicates the measurement noise.

Discussion

We now discuss the microscopics that can explain improved charge offset stability. The charge offset drift is thought to be caused by a broad distribution of electrically active defects associated with amorphous tunnel barriers or gate dielectrics fabricated by conventional thermal oxidation[13,17,36]. Among these defects, TLSs originating from the initial nonequilibrium structure of are quite common, which is also the predominant decoherence source in superconducting qubits[37]. The exact location of the TLSs in the device that adversely affects the charge offset noise remains uncertain, specifically on whether they reside in the tunnel barriers, in the substrate material, or both[38-40]. Additionally, in a recent paper[32] and unpublished data (private communication with M. D. Stewart, Jr. research group), reductions were observed by adding a poly-Si top gate on bulk silicon SETs and replacing bulk Si with SOI in SETs using metal gates. These results imply that the instability is not the only factor affecting the magnitude of the charge noise, but that deliberate device design can also mitigate defect interactions with quantum dots.

Devices fabricated in the present work did not utilize any geometries expected to mitigate charge offset drift. Therefore, we attribute the significant reduction of charge offset drift to i) the better initial oxide quality achieved in the tunnel barrier using plasma oxidation, and ii) the complete processing within a UHV environment. Firstly, previous studies[25-27] have shown that in plasma oxidation, the Al layer can incorporate much more oxygen in a much shorter time and the oxide is much closer to stoichiometric than in conventional thermal oxidation. In plasma oxidation, the neutrally charged, low energy free radicals are the dominant reactive species that accelerate the oxidation process[25], and our plasma is tuned to optimize production. Therefore, a smaller number of unoxidized Al defects are expected in tunnel barriers produced by plasma oxidation relative to those formed by thermal oxidation. We have previously shown reduced long-term resistance drift on tunnel barrier devices[22], consistent with this picture. Secondly, UHV conditions for contamination control are well established to reduce impurity concentrations[41] and improve surface smoothness[42] in the thin Al film deposition, as well as limiting uncontrolled oxide formation in the as-deposited Al layer before deliberate oxygen plasma treatment and reducing structural defects in the tunnel barriers. We propose that plasma oxidation is more likely to be the dominant underlying cause for the significant reduction, but either mechanism could be significant.

We also implemented plasma oxidized tunnel barriers in SETs fabricated from other materials and measured their long-term charge offset drift. Qualitatively, we see improvements in the charge offset drift compared to the historical thermal oxide data shown in Table 1, but it is not as dramatic as in these aluminum only devices. Example data measured in devices are shown in the supplementary information, however, the process optimization and data are far less complete for these devices.

Finally, the stability of these devices suggests an opportunity to evaluate SETs as charge sensors for MOS (metal-oxide-semiconductor) quantum dot based charge qubits or spin-to-charge conversion in spin qubits. In this application, an abrupt change in , corresponding to a 1 e change on a capacitively-coupled qubit, is used to detect a change in qubit charge configuration. The qubit is typically configured such that a charge transition corresponds to a projective readout of the qubit. However, operationally, the charge sensor is often operated in a constant feedback mode, where instead of change in current, an abrupt change in the gate voltage (charge offset) needed to maintain a constant charge sensor current indicates a charge transition. In order to hypothetically consider W119-C1 as a charge sensor, we set the criterion that the change in the control voltage (charge offset) due to a charge transition must exceed 5 SD (99.97 % readout confidence) of the noise for a period long compared to a measurement. For W119-C1, a SD of over a 10-hour period is 0.011 e (also the uncertainty in Table 1), corresponding to a SD in gate voltage (). Therefore, as long as or , where is the coupling capacitance between the MOS quantum dot and the SET charge sensor and is the total capacitance of the quantum dot, the induced charge change on the charge sensor can be distinguished from background instability with 99.97 % confidence. For a typical silicon MOS quantum dot, the total capacitance is aF and requires aF, which is quite small compared to typical coupling capacitances (for example aF in Ref.[43]). Given the long term stability seen in these devices, this hypothetical operation could be expected to persist for periods week without any retuning events.

In summary, we fabricated novel SET devices incorporating plasma oxidized tunnel barriers in a UHV system. Much improved charge offset stabilities are observed in these devices in multi-day measurements, in contrary to the large charge offset drift measured from historical devices using typical, thermally oxidized tunnel barriers. Numerical results demonstrate this improvement quantitatively. Two factors combine to suppress the TLS defects in the tunnel barriers: i) Plasma oxidation, which is a more efficient oxide process and can provide better initial oxide quality, and ii) the UHV environment, which can drastically reduce contamination in the entire fabrication process and preserve the quality of the formed tunnel barriers. Future experiments using thermal oxidation in the UHV environment could separate the impacts of these two possibilities. We speculate that there is some overlap between i) the class of slow defects (time scale: hours or days) that generate slow charge offset drift and ii) the class of faster defects (time scale: microseconds) that lead to decoherence from relaxation or dephasing. For this reason, success in suppressing time instabilities in may pave the way to reducing some decoherence sources associated with [9,10] and enabling expanded implementation within quantum computation systems.

Methods

In order to reduce the fabrication time and increase volume, the macroscopic contact electrodes and interconnects are fabricated first by wafer-scale photolithography, sputter deposition of 10 nm titanium and 50 nm gold, and a subsequent lift-off process. The device fine structures are fabricated by double angle, shadow evaporation techniques[29] using polymethyl methacrylate (PMMA) and methyl methacrylate (MMA) double-layer stencil masks patterned by high-resolution e-beam lithography. All of the steps leading up to deposition of the fine structure are performed ex situ in a nanofabrication facility. Once the large-scale fanout and nano-scale lithographic stencils are complete, the wafers are loaded into a system of UHV chambers with a base pressure of equipped with deposition and plasma oxidation capability for the formation of fine structures. By combining e-beam lithography with photolithography, the total lithographic exposure time is for a 75 mm wafer with 100 devices.

Supplementary Information.