Sounghun Shin1, Yoontae Jung2, Soon-Jae Kweon2, Eunseok Lee2, Jeong-Ho Park3, Jinuk Kim2, Hyung-Joun Yoo2, Minkyu Je2. 1. Foundry Business, Samsung Electronics Co., Ltd., Hwaseong-si, Gyeonggi-do 18448, Korea. 2. School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon 34141, Korea. 3. System LSI Business, Samsung Electronics Co., Ltd., Hwaseong-si, Gyeonggi-do 18448, Korea.
Abstract
This paper presents a reconfigurable time-to-digital converter (TDC) used to quantize the phase of the impedance in electrical impedance spectroscopy (EIS). The TDC in the EIS system must handle a wide input-time range for analysis in the low-frequency range and have a high resolution for analysis in the high-frequency range. The proposed TDC adopts a coarse counter to support a wide input-time range and cascaded time interpolators to improve the time resolution in the high-frequency analysis without increasing the counting clock speed. When the same large interpolation factor is adopted, the cascaded time interpolators have shorter measurement time and smaller chip area than a single-stage time interpolator. A reconfigurable time interpolation factor is adopted to maintain the phase resolution with reasonable measurement time. The fabricated TDC has a peak-to-peak phase error of less than 0.72° over the input frequency range from 1 kHz to 512 kHz and the phase error of less than 2.70° when the range is extended to 2.048 MHz, which demonstrates a competitive performance when compared with previously reported designs.
This paper presents a reconfigurable time-to-digital converter (TDC) used to quantize the phase of the impedance in electrical impedance spectroscopy (EIS). The TDC in the EIS system must handle a wide input-time range for analysis in the low-frequency range and have a high resolution for analysis in the high-frequency range. The proposed TDC adopts a coarse counter to support a wide input-time range and cascaded time interpolators to improve the time resolution in the high-frequency analysis without increasing the counpan class="Chemical">ting clock spn>eed. When the same large interpn>olation factor is adopn>ted, the cascaded time interpn>olators have shorter measurement time and smaller chipn> area than a single-stage time interpn>olator. A reconfigurable time interpn>olation factor is adopn>ted to maintain the phase resolution with reasonable measurement time. The fabricated TDC has a peak-to-peak phase error of less than 0.72° over the inpn>ut frequency range from 1 kHz to 512 kHz and the phase error of less than 2.70° when the range is extended to 2.048 MHz, which demonstrates a compn>etitive performance when compn>ared with previously repn>orted designs.