| Literature DB >> 32005802 |
Guanhua Yang1, Yan Shao2,3, Jiebin Niu1, Xiaolei Ma4,5, Congyan Lu1, Wei Wei1,4, Xichen Chuai1, Jiawei Wang1, Jingchen Cao1, Hao Huang6, Guangwei Xu1, Xuewen Shi1, Zhuoyu Ji1, Nianduan Lu1, Di Geng1, Jing Qi2, Yun Cao2, Zhongliu Liu2, Liwei Liu3, Yuan Huang2, Lei Liao6, Weiqi Dang7, Zhengwei Zhang7, Yuan Liu7, Xidong Duan7, Jiezhi Chen4, Zhiqiang Fan7, Xiangwei Jiang7, Yeliang Wang8,9, Ling Li10, Hong-Jun Gao2, Xiangfeng Duan11, Ming Liu12.
Abstract
In atomically-thin two-dimensional (2D) semiconductors, the nonuniformity in current flow due to its edge states may alter and even dictate the charge transport properties of the entire device. However, the influence of the edge states on electrical transport in 2D materials has not been sufficiently explored to date. Here, we systematically quantify the edge state contribution to electrical transport in monolayer MoS2/WSe2 field-effect transistors, revealing that the charge transport at low temperature is dominated by the edge conduction with the nonlinear behavior. The metallic edge states are revealed by scanning probe microscopy, scanning Kelvin probe force microscopy and first-principle calculations. Further analyses demonstrate that the edge-state dominated nonlinear transport shows a universal power-law scaling relationship with both temperature and bias voltage, which can be well explained by the 1D Luttinger liquid theory. These findings demonstrate the Luttinger liquid behavior in 2D materials and offer important insights into designing 2D electronics.Entities:
Year: 2020 PMID: 32005802 PMCID: PMC6994668 DOI: 10.1038/s41467-020-14383-0
Source DB: PubMed Journal: Nat Commun ISSN: 2041-1723 Impact factor: 14.919
Fig. 1Edge states conductance quantification.
a Optical image of monolayer MoS2 FETs with inner probes (V1–V6) to sense voltage drop within channel. The scale bar is 10 μm. b Output (–) curves of monolayer MoS2 FET at 250 K with gate voltages 10 to 60 V. c The transfer curves (–) in MoS2 device measured at V from 250 to 6.3 K. d The ratios of edge conductance (Gedge) to total conductance (Gtotal) over large temperature and gate voltage range based on the experimental measurements as described in the Supplementary Note 1.
Fig. 2SPM characterization of monolayer MoS2 islands on HOPG.
a Schematic of SPM measurements process. b AFM image of a typical triangular MoS2 island, showing no obvious brightness differences between the edge and the bulk. The profile line (yellow) shows an apparent height of 0.70 nm of the triangular flake, corresponding to the single-layer MoS2 feature. c STM image of the triangular MoS2 island grown alongside the edge of the substrate terrace, clearly showing the electronic edge states with a brim of very high conductance along the island edges. The profile line (yellow) also shows a significant protrusion at the edge. The apparent height of the triangular flake is 0.72 nm, consistent with the AFM measurement in b. d Zoomed-in STM image of the area indicated by the dark-blue rectangle in c. Inset: atomic resolution image of MoS2 obtained from the area indicated by the white dashed square. e dI/dV spectra taken across the MoS2 edge from HOPG to the bulk MoS2. The color of the curves is consisted with the color of marked positions in the inset. The tunneling spectrum (#3) acquired at the MoS2 edge shows clearly electronic states (marked by pink) around Fermi level, revealing its metallic feature. STM scanning parameters: U = −1.0 V, I = 100 pA (c) and (d) U = −1.0 V, I = 800 pA for the inset.
Fig. 3Calculations of charge transport on edge state of monolayer MoS2.
a Schematic of monolayer MoS2 FET (Uppermost row); side view (Middle row) and top view (Lowest row) of monolayer MoS2. The isosurface plots for transmission eigenstates of the MoS2 channel at the k-point Γ(0,0) and the energy of 0.05 eV under the conditions of VDS = 0 V and VG = 0 V in b, and VDS = 0 V and VG = 0.5 V in c. The evolving of the carriers in bulk is revealed as highlighted by the red ellipse in b and c, although only a small gate voltage (0.5 V) is applied in simulation.
Fig. 4SKPFM measurement of monolayer MoS2 FET.
a Optical image of the MoS2 FET device. The white rectangle region is the one selected for SKPFM measurement. b AFM image of the selected region. c Local potential map of the selected region at the bias voltage of VDS = 8 V and VG = 0 V. Line scans of the potential both across the edge (Line A) and the bulk (Line B) of the MoS2 flake. d Voltage potential comparison between the experimental data and simulation data. The experimental potential difference at the edge is 524 mV (Circles in Line A) and the difference at the bulk is 137 mV (Circles in Line B). The significant high potential at the edge indicates that charges flow at edge under the given bias voltage. The simulation results (Solid line) match well with the experimental results. e Simulated potential mapping of MoS2 channel based on the finite-element method, consistent with the experimental mapping in c.
Fig. 5Evidence of Luttinger liquid transport in monolayer MoS2 FET.
a Typical (IDS–V12) curves measured under VG = 60 V, varying temperature from 350 to 6.3 K. b The (IDS–V12) below 50 K are shown, illustrating clear nonlinear charge transport behavior in monolayer MoS2 FET. c Power law relation of conductance G with temperature (G ∼ Tα) at low bias V12 = 0.1 V, obtaining a fitting exponent α = 2.2 from the red fitting curve. d Power law relation of the current with the voltage at low temperature T = 6.3 K, having a fitting exponent β = 2.2. e The output transport data and the corresponding curve plotted by IDS/T1+α against qV12/kBT under the gate voltage of VG = 60 V. The nonlinear (IDS–V12) data scale well onto a universal curve over the temperature range from 50 to 6.3 K. The fitting curve indicates nonlinear Luttinger liquid behavior. f (IDS–V12) data scale onto the universal curve replotted as IDS/T1+α versus qV12/kBT under other gate biases: VG = 30, 40, and 50 V, respectively.