An Energy-Efficient CMOS Dual-Mode Array Architecture for High-Density ECoG-Based Brain-Machine Interfaces.

This article presents an energy-efficient electrocorticography (ECoG) array architecture for fully-implantable brain machine interface systems. A novel dual-mode analog signal processing method is introduced that extracts neural features from high- γ band (80-160 Hz) at the early stages of signal acquisition. Initially, brain activity across the full-spectrum is momentarily observed to compute the feature weights in the digital back-end during full-band mode operation. Subsequently, these weights are fed back to the front-end and the system reverts to base-band mode to perform feature extraction. This approach utilizes a distinct optimized signal pathway based on power envelope extraction, resulting in 1.72× power reduction in the analog blocks and up to 50× potential power savings for digitization and processing (implemented off-chip in this article). A prototype incorporating a 32-channel ultra-low power signal acquisition front-end is fabricated in 180 nm CMOS process with 0.8 V supply. This chip consumes 1.05  μW (0.205  μW for feature extraction only) power and occupies 0.245 [Formula: see text] die area per channel. The chip measurement shows better than 76.5-dB common-mode rejection ratio (CMRR), 4.09 noise efficiency factor (NEF), and 10.04 power efficiency factor (PEF). In-vivo human tests have been carried out with electroencephalography and ECoG signals to validate the performance and dual-mode operation in comparison to commercial acquisition systems.