Shape-controlled single-crystal growth of InP at low temperatures down to 220 °C.

III-V compound semiconductors are widely used for electronic and optoelectronic applications. However, interfacing III-Vs with other materials has been fundamentally limited by the high growth temperatures and lattice-match requirements of traditional deposition processes. Recently, we developed the templated liquid-phase (TLP) crystal growth method for enabling direct growth of shape-controlled single-crystal III-Vs on amorphous substrates. Although in theory, the lowest temperature for TLP growth is that of the melting point of the group III metal (e.g., 156.6 °C for indium), previous experiments required a minimum growth temperature of 500 °C, thus being incompatible with many application-specific substrates. Here, we demonstrate low-temperature TLP (LT-TLP) growth of single-crystalline InP patterns at substrate temperatures down to 220 °C by first activating the precursor, thus enabling the direct growth of InP even on low thermal budget substrates such as plastics and indium-tin-oxide (ITO)-coated glass. Importantly, the material exhibits high electron mobilities and good optoelectronic properties as demonstrated by the fabrication of high-performance transistors and light-emitting devices. Furthermore, this work may enable integration of III-Vs with silicon complementary metal-oxide-semiconductor (CMOS) processing for monolithic 3D integrated circuits and/or back-end electronics.

Due to superb electronic and optoelectronic properties, III–V compound semiconductors have been widely used for high-performance photonic and electronic devices. Traditional techniques for growing III–V thin films employ the vapor–solid (VS) growth scheme, e.g., metalorganic chemical vapor deposition (MOCVD) and molecular-beam epitaxy (MBE). However, the adsorbed gas reactants can suffer from low diffusivity on the surface of the growing film compared to the condensation rate when grown at low temperatures and/or on nonepitaxial substrates, leading to polycrystalline or amorphous films instead of single-crystalline ones. In this regard, liquid-phase growth methods have proven to be promising alternatives including vapor–liquid–solid (VLS) (1–8), liquid-phase epitaxy (9), and rapid melt growth (10, 11). In the specific case of VLS growth, a transient liquid phase is introduced that facilitates the kinetics of nucleation and crystal growth, providing an inherent advantage over VS processes and enabling large-area thin-film crystalline growth, even on amorphous substrates (7). In principle, introducing an intermediate liquid phase should allow the growth temperature to be lowered as long as the liquid still has a finite solubility of the gas reactant. For example, InP growth should be achievable down to the melting point of indium (156.6 °C), as liquid indium has a finite solubility of phosphorus at that temperature (12). By separating the phosphine cracking from substrate heating (Fig. 1), we show that the growth temperature of InP can be down to 220 °C.

Fig. 1.

LT-TLP growth of InP. (A) Schematic of the LT-TLP process where the sample is placed at low temperatures while the gas is cracked at high temperature. S indicates the solid phase; L, liquid. (B) Schematic of the InP nucleation and growth processes. (C–E) Images of as-grown InP patterns on n+Si/SiO2, ITO-coated glass, and peeled polyimide.

Fig. 1 depicts a schematic of the growth process. Prior to growth, patterned indium metal encapsulated by SiOx was formed on top of a thin nucleation layer (1 to 5 nm MoOx or 10 nm Al2O3; details in ). The InP growth was then conducted in a standard tube furnace flowed with PH3 as the phosphorus source, diluted by H2 at a controlled pressure. A source cracking zone with a center temperature of 550 °C allowed the phosphine gas to be converted efficiently into P2 and P4 reactants (13), while a calibrated temperature gradient to the substrate prevented phosphorus condensation. Samples were placed at the end of the temperature gradient along the low-temperature region. In this work, the substrate temperature was systematically varied between 220 and 370 °C. During the growth process, phosphorus diffuses through the SiOx cap and supersaturates the encapsulated liquid indium, resulting in InP nucleation and subsequent growth. Notably, once an InP nucleus is formed in liquid indium, a large phosphorus depletion zone is formed within the vicinity of the nucleus, thus preventing further nucleation events in close proximity. The size of the depletion zone depends on the ratio of the diffusion coefficient of phosphorus in liquid indium to the flux of incoming phosphorus through the solid SiOx cap (7). In the past, we have shown large depletion zones up to 500 µm in lateral dimension by controlling various process parameters such as phosphorus partial pressure (5). By patterning indium into lateral dimensions smaller than this depletion zone, a high probability of single-crystal patterned growth is enabled with the probability dependent on the ratio of the depletion length to feature size.

Optical images of patterned InP circles (thickness, ∼300 nm; diameter, 3 to 7 µm) grown on Si/SiO2 at 270 °C are shown in Fig. 1. The low growth temperature characteristic of the LT-TLP method allows for direct growth of InP on an unprecedented range of substrates. As a proof of concept, InP patterns were directly grown on indium-tin-oxide (ITO)-coated soda-lime glass (Fig. 1) and polyimide substrates (Fig. 1), both of which are thermally incompatible with traditional III–V deposition techniques such as MBE and MOCVD. While 220 °C is the lowest growth temperature used in this work to assess material quality, we note that nucleation and growth occur at temperatures as low as 180 °C (), demonstrating the flexibility of this method for a wide range of applications in flexible and transparent electronics. In the past several years, various efforts have explored development of low-temperature grown inorganic semiconductor thin films, including metal oxides and a-Si (14, 15) for glass and plastic-based electronics. The work here presents a viable low-temperature growth technique for III–V compound semiconductors.

X-ray diffraction was performed to identify the zincblende phase of InP patterns grown by low-temperature templated liquid phase (LT-TLP) (). The cross-sectional transmission electron microscopy (TEM) image shown in Fig. 2 clearly depicts the crystalline nature of the InP pattern grown atop an amorphous substrate (MoOx/SiO2). High-resolution TEM and selected area electron diffraction (SAED) images display twin orientation across the exposed crystal face (Fig. 2 and ). Similar twin boundaries and stacking faults have also been observed in previous reports regarding InP structures grown at higher temperatures (16). Twin-corrected electron backscatter diffraction (EBSD) was further used to examine the lateral dimensions of the crystal domains in our grown samples. A scanning electron microscope (SEM) image of patterned InP crystals grown at 270 °C is shown in Fig. 2, with a corresponding EBSD map (Fig. 2 and ). The majority of the InP circles with diameters of 3 µm contain a single-crystal domain, with the probability of additional domains per pattern increasing with feature size (). To better understand this behavior, nucleation density for unpatterned thin-film growth was extracted as a function of growth temperature (; a detail discussion is in ). By assuming a hexagonal packing geometry (6), the crystal-domain spacing can also be extracted and shows an exponential relationship with growth temperature. A maximum domain size of 8 µm is obtained for the growth temperature 270 °C and PH3 partial pressure 0.5 torr, consistent with the EBSD measurement (Fig. 3 and ).

Fig. 2.

Characterization of single-crystalline InP. (A) TEM. (B) HRTEM, and (C) SAED of InP crystals grown at 270 °C substrate temperature. (D) SEM image and (E) corresponding EBSD map for 3-µm circles of InP grown at 270 °C. (F) Internal QY for LT-TLP InP grown at 220 and 370 °C. Note that more than 5 samples were measured for each growth temperature. (G) Normalized steady-state PL spectra for LT-TLP InP grown at different temperatures.

Fig. 3.

t-EL devices on silicon substrate. (A) Schematic structure of the t-EL device. The growth temperature of InP is 270 °C using an insulating Al2O3 layer for nucleation. (B) Time-resolved EL spectrum for 1 full cycle of a t-EL device in operation. (C) EL and PL spectra for a t-EL InP device. (D) Voltage and (E) frequency dependence of a representative device. (F) EL image of a device modulated with a Vg = ±10 V, f = 20-MHz square wave. (Inset) An optical microscope image of a device.

Photoluminescence (PL) measurements were performed to further characterize the material quality of our crystals (17). In Fig. 2, normalized PL spectra are plotted for growth temperatures from 220 to 370 °C. The Urbach tails derived from the spectra show that the Urbach energies of the crystals grown at low temperature are comparable to the values from 500 to 535 °C growth and bulk n-type single-crystal wafer references (7) (), indicating a low density of defect states near the band edges. Moreover, the maximum PL quantum yield (QY) measured was 10 ± 2% for the samples grown at 220 °C without surface passivation or cladding layers (Fig. 2), demonstrating the high-quality nature of crystals produced by the LT-TLP method. The corresponding normalized PL spectra as a function of excitation power do not show any strong change in spectral shape, which is also indicative of a low defect density (). The QY also shows minimal dependence on the growth temperature in the explored range of 220 to 370 °C (Fig. 2). Overall, optical measurements suggest high material quality, even for the unprecedented low growth temperatures used here.

InP light-emitting devices were fabricated to realize the potential of the LT-TLP method for optoelectronic applications. Here we employed the transient electroluminescent (t-EL) device structure, where high injection levels for bright EL are achieved without the need of forming simultaneous ohmic contacts to electrons and holes (18). InP was grown on n+ Si (gate)/SiO2 (gate oxide) and contacted by an evaporated Ti/Au (source) electrode (Fig. 3). During t-EL operation, the source is grounded and a square-wave voltage (V) is applied to the gate. Efficient bipolar carrier injection is achieved during each voltage transition. The injected carriers then recombine with the stored charges from the previous cycle, resulting in EL emission. This device architecture has been previously reported in other material systems including monolayer semiconductors (18). The transient EL can be visualized by the time-resolved EL spectrum in Fig. 3, with emission transients closely following the rising and falling edges of VG. The transient emission displays greater intensity on the rising edges of each pulse, indicating a lower injection barrier for electrons.

The EL spectrum for a t-EL device closely resembles the PL emission spectrum (Fig. 3). The dependence of EL intensity with respect to gate bias and frequency are presented in Fig. 3 , respectively. EL is observed when VG > 2.5 V, where the turn-on voltage depends on the bandgap of the InP (1.3 eV) and parasitic resistances in the device. Emission intensity increases linearly with frequency, reflecting the pulsed nature of t-EL operation. EL imaging of the t-EL device is shown in Fig. 3. EL is observed near the source contacts, and the emission region laterally extends from the contact edge by 7 to 9 μm. This successful demonstration indicates a promising path toward the implementation of TLP-grown InP in displays and future photonic applications, even on low-thermal-budget substrates.

We also examined the electronic quality of the InP to determine the viability of this method for electronic applications. The measured Hall mobilities as a function of growth temperature are shown in Fig. 4. As-grown InP was patterned into 7 × 7-µm2 squares to avoid grain-boundary influence on measurements (see and ). The average Hall mobility µH is 743 cm2 V−1⋅s−1 for 370 °C and 236 cm2 V−1⋅s−1 for 235 °C, for an electron concentration in the range 1015 through 1016 cm−3. The highest µH measured for the 370 °C case is 862 cm2 V−1⋅s−1, a value approaching 30% of mobilities reported for InP wafers with similar doping concentrations (19, 20).

Fig. 4.

Electronic characterization of LT-TLP InP. (A) Average Hall mobility vs. temperature, with error estimated by measurement geometry indicated by whiskers. Note that more than 3 devices were measured for each growth temperature. (B) Schematic and optical images (Bottom Right) before gate deposition of single-microwire transistors. (C and D) Transistor characteristics of an InP transistor with W/L 1 µm/20 µm and thickness ∼80 nm. InP was grown at 370 °C.

Field-effect transistors were fabricated using patterned InP microwires as the channel (W/L, 0.25 to 1 µm/4 to 20 µm; thickness, ∼80 nm). ZrO2/Ni/Au was deposited as the top gate and Pd/Ge contacts were formed as source/drain (Fig. 4, fabrication details in ). ID-VG and ID-VD characteristics for a device are presented in Fig. 4 . The device exhibits ION/IOFF ratio of 1.5 × 104 and ION of 14 µA/µm at VG = VD = 3 V. After correcting for contact resistance (see ) (20), we extracted a peak effective electron mobility of 663 cm2 V−1⋅s−1. This effective mobility is comparable with average Hall mobilities for the same growth temperature, and similar to the mobility previously reported for wires grown at 500 to 535 °C (7).

In addition to applications for plastic and glass electronics and lighting, LT-TLP could also present a viable approach toward monolithic integration of high-mobility III–V semiconductors on silicon complementary metal-oxide-semiconductor (CMOS) for 3D integrated circuits and back-end electronics. In this regard, the semiconductor must be processed at temperatures below 400 °C, which is the thermal budget of silicon CMOS (21). Low-temperature growth of high-quality semiconductors has proven extremely challenging (), thus to date limiting the practical realization of such architectures. LT-TLP growth directly overcomes this fundamental problem. This presents an important future research direction employing LT-TLP.

In summary, we present single-crystalline InP patterned growth at ultralow temperatures down to 220 °C. The crystals exhibit high electron mobility and PL QY, notably without surface passivation or cladding layers. Furthermore, the method presented in this work is compatible with a wide range of substrates without epitaxial growth and transfer requirements (22–25), thus dramatically broadening the application domain of III–V semiconductors. While the patterned structures are single crystalline, the current work does not provide for orientation control. In the future, by controlling the surface energies of the substrate, it may be possible to preferentially nucleate a specific orientation. Additionally, the approach could be universal to other III–V compound semiconductors. In this regard, future exploration of LT-TLP growth of other indium- and gallium-based compounds, including ternary alloys, would be of interest. Finally, while a temperature gradient was used to activate the precursor, in the future, plasma could also be used to perform a similar role in a more controlled environment.

Materials and Methods

Temperature Gradient Calibration.

Prior to growth, the temperature gradient from furnace center to furnace end was calibrated using a thermocouple in situ in order to closely approximate the substrate temperature for our typical center set point of 550 °C. The thermocouple was inserted inside the tube via feedthrough, and temperatures were measured under gas flow at different positions. Substrate placement for each growth temperature was dictated by the temperature reading for all calibration conditions.

Substrate Preparation and Growth Method.

The substrates used were 50-nm SiO2/n+ Si, commercial ITO-coated soda-lime glass (12-Ω⋅cm square float glass, Sigma-Aldrich), and polyimide substrates prepared using SiO2/n+ Si handle wafers and a spun polyimide film (HD MicroSystems, polyimide-2525) cured at 300 °C. Photolithography was used to pattern the substrate, prior to evaporating a thin nucleation layer of material such as MoOx, followed by indium and confining caps of SiOx (). The substrate was then heated in a tube furnace in hydrogen to the desired substrate temperature and exposed to PH3 gas diluted in H2 to a desired partial pressure. Growth time for patterned InP was 30 to 60 min. The resulting phosphorized films were then etched in hydrofluoric acid to remove the SiOx caps before further processing. Insulating Al2O3 nucleation layers were used for the t-EL devices and MoOx nucleation layers were used for all other structures shown in this study. Typical film thicknesses, measured by quartz crystal monitor, were 5 to 10 nm for e-beam evaporated Al2O3, 0.3 to 1.3 nm for thermally evaporated MoOx, 40 to 150 nm for e-beam evaporated indium, and 10 to b50 nm for e-beam evaporated SiOx side caps.

EBSD Measurement.

EBSD measurements were performed using an FEI Quanta field emission gun SEM and an Oxford EBSD detector with a fluorescent screen. Oxford Aztec and Tango software were used to analyze the EBSD patterns and maps, and to generate inverse pole figure color schemes for the data shown. Twin-boundary correction was performed in the same software by removing <111> 60° rotational boundaries and replotting grain surface orientation.

Optical Characterization.

For PL measurement, a 514-nm Ar ion laser was used to excite each sample at the same power (80 µW), with light collected by a 50× objective lens, passed through a 550-nm long-pass filter, and analyzed by a spectrometer and Si charge-coupled device. PL QY and EL data for this study were collected using a homebuilt optical system (18). Briefly, PL QY measurements were calibrated using a ThorLabs SLS201 calibration lamp reflected off a Lambertian surface under the objective, followed with the measurement of system response by collection of the diffusely reflected excitation beam by the system spectrometer and cross-calibration with the lamp.

t-EL Device Fabrication and Measurement.

All transient EL devices were fabricated using InP squares grown at 270 ± 10 °C. Ti/Au contacts patterned by photolithography were used for a typical device, with a forming gas anneal at 270 °C for ∼10 min to improve the contact–InP interface. For all devices, a lower than normal contact anneal temperature was chosen to fit the maximum growth temperature, maintaining the low-T process window. Measurements were performed in a similar manner to ref. 18, with the Ti/Au source grounded and a square-wave excitation applied to the n+ silicon back gate. Al2O3 was used as an insulating nucleation layer. The square wave was generated by a bipolar-based Agilent 33522A waveform generator, and EL images presented were collected using a microscope system and an Andor Luca camera with excitation in ambient environment.

Hall Device Fabrication and Measurement.

Hall measurement devices were fabricated in a square configuration using MoOx nucleation layers less than 1.4 nm and as-grown thicknesses of ∼85 to 90 nm as estimated by atomic force microscopy and cross-sectional TEM measurements. A square Van der Pauw configuration with devices in the 7 through10-µm range was chosen to limit fabrication and growth complexity, and electron beam lithography was used to pattern contacts to avoid alignment offset error. A Pd/Ge metallization was used to give linear contact behavior for all devices, with rapid thermal annealing in a 5% H2/95% N2 ambient to improve contact resistance. The temperature for this step was maintained at a maximum of 10 °C above the growth temperature to avoid annealing effects on the electrical parameters. An Ecopia HMS 300 Hall measurement tool was used with a ∼0.55-T permanent magnet for the presented measurements, with currents in the 10 through 100-nA range. Further details on the measurements and cross-checking procedures, along with geometrical error estimation, can be found in .

Transistor Fabrication and Measurement.

Transistor devices were fabricated using InP grown at 370 ± 10 °C, given the higher measured Hall mobility at this growth temperature. First, microwires were patterned using e-beam lithography with widths between 250 and 1000 nm. Indium substrates were prepared as previously described, with MoOx nucleation layer thickness less than 1.2 nm and indium thickness ∼30 to 40 nm. Source and drain contacts of Pd/Ge were then patterned by photolithography on the ∼75 to 85-nm as-grown films, with channel lengths between 4 and 20 µm. To minimize contact resistance, an optimized Pd/Ge rapid thermal alloy process was used in a forming gas ambient, in order to dope a thin surface layer under the contact and provide a spike-free alloyed contact interface with the PdGe alloy metal. The optimum contact annealing conditions were a 225 °C/3 min initial alloy step followed by a 390 °C/3 min anneal step. Following contact annealing, a 15-nm ZrO2 gate oxide a was thermally deposited at 200 °C using a Cambridge Nanotech atomic layer deposition system and tetrakis (ethylmethylamido) zirconium Zr precursor with water as the oxidizer. The gate metal was then patterned by photolithography, with a Ni/Au gate used to compare to prior InP devices.

Data Availability.

All datasets have been deposited in Dryad: https://datadryad.org/stash/dataset/doi:10.6078/D15H5W.