| Literature DB >> 31877890 |
Dongliang Chen1,2, Liang Yin1,2, Qiang Fu1,2, Wenbo Zhang1,2, Yihang Wang1,2, Guorui Zhang1,2, Yufeng Zhang1,2, Xiaowei Liu1,2,3.
Abstract
The EM- Σ Δ (electromechanical sigma-delta) approach is a concise and efficient way to realize the digital interface for micro-electromechanical systems (MEMS) accelerometers. However, including a fixed MEMS element makes the synthesizing of the EM- Σ Δ loop an intricate problem. The loop parameters of EM- Σ Δ can not be directly mapped from existing electrical Σ Δ modulator, and the synthesizing problem relies an experience-dependent trail-and-error procedure. In this paper, we provide a new point of view to consider the EM- Σ Δ loop. The EM- Σ Δ loop is analyzed in detail from aspects of the signal loop, displacement modulation path and digital quantization loop. By taking a separate consideration of the signal loop and quantization noise loop, the design strategy is made clear and straightforward. On this basis, a discrete-time PID (proportional integral differential) loop compensator is introduced which enhances the in-band loop gain and suppresses the displacement modulation path, and hence, achieves better performance in system linearity and stability. A fifth-order EM- Σ Δ accelerometer system was designed and fabricated using 0.35 μ m CMOS-BCD technology. Based on proposed architecture and synthesizing procedure, the design effort was saved, and the in-band performance, linearity and stability were improved. A noise floor of 1 μ g / Hz , with a bandwidth 1 kHz and a dynamic range of 140 dB was achieved.Entities:
Keywords: MEMS; accelerometer; electromechanical sigma-delta; sensor interface
Year: 2019 PMID: 31877890 PMCID: PMC6982865 DOI: 10.3390/s20010091
Source DB: PubMed Journal: Sensors (Basel) ISSN: 1424-8220 Impact factor: 3.576
Figure 1The architecture of the EM- system.
Figure 2The architecture of the third-order electrical loop filter.
Figure 3The abstracted signal flow diagram of the whole system.
Figure 4The signal flow diagram of the signal loop.
Figure 5TA frequency response comparison with different type of compensator: (a) the frequency response of loop compensator ; (b) the frequency response of total loop gain .
Figure 6The simplified signal flow diagram to emphasize the local positive feed-forward path.
Figure 7The value of with the mismatch factor at different loop gain values ().
Figure 8The waveform in front of electrical modulator: (a) with a traditional phase lead compensator; (b) with the proposed PID (proportional integral differential) compensator.
Figure 9The signal flow diagram of the quantization noise loop.
Figure 10Test results of digital quantization noise loop: (a) noise transfer function (NTF) response; (b) root locus of the quantization noise loop; (c) the amplitude of each integrator output.
Figure 11The top level implementation of the fifth-order EM- loop.
Figure 12The circuit diagram of the front-end amplifier.
Figure 13The signal flow diagram of the quantization noise loop.
Figure 14The micro-photograph of the die of the ASIC.
Figure 15The photograph of the testing mother board with a ASIC and MEMS accelerometer mounted.
Figure 16The step response of the EM- system: (a) the step response of rising edge; (b) the step response of the falling edge.
Figure 17The nonlinearity test result of the EM- accelerometer.
Figure 18The input referred noise spectrum density of the proposed EM- accelerometer.