Variability Improvement of TiO x /Al2O3 Bilayer Nonvolatile Resistive Switching Devices by Interfacial Band Engineering with an Ultrathin Al2O3 Dielectric Material.

Variability control over the resistive switching process is one of the key requirements to improve the performance stability of the resistive random access memory (RRAM) devices. In this study, we show the improvement of the variability of the resistive switching operation in the TiO x /Al2O3 bilayer RRAM devices. The achievement is based on the thickness engineering of the Al2O3 layer. A thick Al2O3 dielectric actively takes part to control the resistive switching behavior; on the contrary, the ultrathin layer of Al2O3 behaves as the tunnel barrier in the structure. At lower voltage, the low resistance state conductions follow the trap-assisted tunneling and Fowler-Nordheim tunneling for the thick and thin Al2O3 RRAMs, respectively. Finally, the variation control in device forming, SET voltage distribution, high resistance state, low resistance state, and resistance ratio is achieved with the TiO x /Al2O3 bilayer RRAM devices by interfacial band engineering with an ultrathin Al2O3 dielectric material.

Introduction

Advancement of nonvolatile memories in device scaling with amplified performance adds to the prospect of enhancing the horizon of new applications.[1,2] The physical and practical limitations are busting the distinct and individual alternatives with exciting architectures.[3−5] Attractive resistive random access memory (RRAM) in a simple metal–insulator–metal form is an emerging device in which electrical resistance (R) can be rearranged within the high resistance state (HRS) and the low resistance state (LRS).[6] Several features such as simple design, low power operation, excellent scalability, and so forth make the RRAM an important candidate for future nonvolatile memory technology.[7] The RRAM devices are equally useful for ultrahigh density memory application as well as for a brain-inspired computing system.[8−11] In any form of the application, stable resistive switching (RS) is a basic need for the successful implementation of RRAM devices in real life.[12,13] So far, uniformity in RS operation or, in other words, variability control of the RRAM devices is one of the major concerns. On the other hand, the material is a vital part to design RS devices. There are several established materials such as HfO2,[14,15] Ta2O5,[16,17] TiO2,[18,19] Al2O3,[20,21] and so forth that are capable of executing good RS in the RRAM devices. These RS devices are further categorized in the electrochemical memory type or valance change memory (VCM) type following the conducting nanofilament (CNF) formation in the RRAM based on cation migration or anion migration.[22] It is really difficult to control the formation of CNF at each RS operation. The RS variation over cycles is a common phenomenon in RRAMs. Several reports show that the improvement of switching uniformity is possible by structure engineering with external doping,[23,24] inserting nanocrystals (NCs) in the switching stack,[25,26] annealing the RRAM,[27] and also by controlling proper operating conditions.[28,29] Improvement of the TiO2 RRAM by inserting Ru–NCs is possible by choosing proper thickness for the NCs for the right location.[30] Misha et al.[24] had reported the improvement of the TaO RRAM by nitrogen doping after going through several trial and error processes with various doping concentrations. Annealing can improve the variability control, but at the same time, it can increase the thermal budget and the fabrication cost of the RRAM. Banerjee et al.[21] had reported that the improvement of the RS operation is possible by choosing appropriate polarity for the applied bias. Therefore, it is concluded that the variability improvement is possible after going through heartfelt efforts which is time-consuming and at the same time increasing the overall fabrication and operation cost. The need of time describes the fact that it is an important task to find out a simple way to improve the uniformity of the RS behavior of RRAM devices with a simple CMOS-friendly stack design which can be implemented for the further nonvolatile memory applications.

In this work, we have investigated the simple, cost-effective, time-saving process to improve the variability of TiO/Al2O3-based VCM-type RRAM devices. As the name suggests, the CNF in the devices is based on the oxygen vacancy (VO)-type anion migration process. In our previous work, we have reported the high-compliance current-dependent Magneli-type CNF formation in the TiO/Al2O3 bilayer.[8] In this work, the design was started with an 8 nm thick Al2O3 film and ultimately scaled to an ultrathin 2 nm Al2O3 interfacial layer. The 8 nm thick Al2O3 film actively takes part in the RS process, but the 2 nm Al2O3 with a natural large barrier height plays a major role as a tunnel barrier at the interface. The role of Al2O3 as a tunnel barrier material is well-established.[31,32] The variability control in device’s forming voltage, operation voltage, HRS, LRS, and resistance ratio (ζ = HRS/LRS) has been achieved with the TiO/Al2O3 bilayer RRAM devices by interfacial band engineering with an ultrathin Al2O3 dielectric material.

Results

Effect of Interfacial Al2O3 Layer Thicknesses on the RS Performances

The bright-field scanning transmission electron microscopy (STEM) images of the TiN/TiO/Al2O3/IrO RRAM stack is shown in Figure a. The TiN layer is employed as a word line (WL) and IrO as a bit line (BL). The elemental mapping of the RRAM is shown in Figure b–e for Ti, N, O, and Al, respectively. Details of the device fabrication had been discussed in our previous works.[8,10] The interfacial Al2O3 layer was engineered with thickness variation. Three types of devices can be identified as S1, S2, and S3 for 8, 5, and 2 nm of Al2O3, respectively. The stack design is confirmed by the high-resolution transmission electron microscopic (HRTEM) analysis using a JEOL JEM2100F TEM instrument. Figure f shows HRTEM images with different thicknesses of Al2O3 layers. The thickness of TiO is ∼8 nm for all structures. The thicknesses of Al2O3 are found to be ∼8, ∼5, and ∼2 nm, for S1, S2, and S3 RRAMs, respectively. Figure g shows the line scan image and compositions of the S3 RRAM. Interdiffusion of Al2O3 in TiO is observed in the fabricated devices. The intermixing (TiO + Al2O3) oxide is of the Magneli type.[8] After the fabrication processes, the devices were maintained in an initial HRS. Device forming is necessary for the initial distribution of VOs in the RRAM devices. For an easy understanding of the behavior, performance improvement, and the effect of Al2O3 layer thickness, we discuss electrical performances of different structures one by one. To initiate the RS process, the 8 nm Al2O3-based S1 RRAM devices need an initial forming voltage of ∼14 ± 2.731 V. The device-to-device statistical distribution of the forming voltage is shown in Figure S1a. A positive voltage was applied to the BL during the forming processes, and the current level was fixed at 100 μA. After the initial forming, the continuous RS cycles were measured. Figure a shows 100 consecutive RS operations with a positive voltage sweep. The HRS of the S1 RRAM was swept to a comparative LRS with applied voltage from 0 V → +7 V, and the switching process is known as the SET process. The 1st cycle of the process is indicated with a solid circle, and the 100th cycle is indicated with an open circle. The RS direction is indicated with an arrow. After each positive voltage operation, a negative voltage was applied to the BL. Figure b shows the 100 consecutive RS operations with a negative voltage sweep. The LRS of the S1 RRAM was swept to a comparative HRS with an applied voltage from 0 V → −3 V and the switching process is known as the RESET process. The arrow indicates the RS direction. The SET transition is possible because of the formation of the VO CNF, and the RESET transition is possible because of the rupture of the CNF. The continuous 100 RS cycles depict a nonuniform nature of the CNF in the S1 RRAM. The difference in the 1st cycle and the 100th cycle is quite visible. In the first cycle, the transition from the HRS to the LRS is dominant with one jump from the HRS to the LRS. However, at the 100th cycle, several intermediate jumps change the current from the HRS to the LRS. To understand it more clearly, the cycle-to-cycle variations from the HRS to the LRS are shown in Figure S2. The sudden jumps of resistances are marked with numbers such as ①, ②, ③, and ④. The probability of the CNF broken in two or three places is higher than that of the CNF broken in a single place. Before and after a certain jump, the current always increases; that is, the resistance always decreases with increasing voltages from the HRS to the LRS. Figure a shows the resistance versus voltage (R–V) plot of the 100th cycle. Before reaching the LRS, the HRS arrives at several intermediate resistance states at 8 MΩ, 1.5 MΩ, and 300 kΩ that are marked with R1, R2, and R3, respectively. The inset of Figure a shows the continuous tunneling (CT) effect at the R3 state of the S1 RRAM. After reaching a resistance of 180 kΩ, the final jump of the resistance switches the device to its LRS at 50 kΩ. Different devices show a similar kind of nature. Figure b shows the 100th cycle from 10 randomly chosen S1 RRAMs. All these measurements show that the SET transitions of the S1 RRAM are possible by connecting several broken (likely two to three) CNFs, where charges are transferred by CT followed by discrete tunneling (DT) processes.

Figure 1

TiO/Al2O3 bilayer RRAM devices. The STEM (a) bright-field image of the RRAM design. The elemental mapping of the materials in the system for (b) Ti, (c) N, (d) O, and (e) Al. (f) The HRTEM images of the TiO/Al2O3 bilayer design with different thicknesses of Al2O3, that is, S1: 8 nm, S2: 5 nm, and S3: 2 nm. (g) The line scan data show the validation of the TiO/Al2O3 bilayer design.

Figure 2

I–V characteristics of the S1 RRAM. Consecutive 100 cycles of (a) SET switching and (b) RESET switching.

Figure 3

Continuous and DT in the TiO/Al2O3 bilayer RRAM. The RS process is based on the CT and DT for (a,b) S1 RRAM and (c) S2 RRAM. The broken pieces of CNF are more prominent in the S1 RRAM. (d) S3 RRAM shows a CT nature.

The RS in S2 and S3 RRAMs is a little different than the RS in the S1 RRAM. However, the S2 and S3 RRAMs also need an initial forming step. The device-to-device statistical distribution of the forming voltage is plotted in Figure S1b,c for the S2 and S3 RRAMs, respectively. Similar forming conditions were maintained during measurements. On average, forming voltages of ∼12.3 ± 2.002 and ∼9.6 ± 0.914 V are necessary for the S2 and S3 RRAMs, respectively. After the forming process, the current–voltage (I–V) switching of the S2 RRAM is shown in Figure c. The switching from the HRS to the LRS shows a jump at the voltage of ∼+4 V, followed by a gradual increase in current to the compliance level. In the inset of Figure c, the R–V plot of the sudden jump illustrates a change of the higher resistance of 3 MΩ at point A to the lower resistance of 170 kΩ at point B. After B, the resistance further decreases to the LRS of the device (∼50 kΩ). Unlike S1, S2 RRAM devices might have fewer broken places of CNF. However, no such sudden jump was observed for the S3 RRAM. As shown in Figure d, the I–V and R–V shows the continuous increasing and decreasing nature of the I and R, respectively.

Apart from the switching nature, the changes among different RRAM structures are also observed in the device’s operating parameters, resistance states, and resistance ratio. Figure a shows the voltage to SET (VSET) plotting to show the cycle-to-cycle variation and also device-to-device variation within the same frame. Five devices for each structure were measured for 103 cycles each. The VSET values are found to be ∼5.4 ± 0.92, 4.5 ± 0.40, and 3.5 ± 0.28 V, for S1, S2, and S3, respectively. A large variation of the voltage is observed for the 8 nm Al2O3 S1 RRAM devices. The VSET of the device decreases with the decrease of the thickness of the Al2O3 layer. A good control of the variation is achieved for the S3 RRAM devices as compared to the S1 and S2. The systematic study shows that the resistance states are also different for S1, S2, and S3. Although the scaling symmetry was missing for the LRS, the HRS changed in a fashion similar to that shown in Figure S3. On average, the lower LRS and HRS variations of the S3 RRAM devices are due to the ultrathin 2 nm Al2O3 interface. The variability control can be observed in the ζ, as shown in Figure b. The devices show ζ values of ∼21, 13, and 10 for the S1, S2, and S3 RRAM, respectively. However, larger variations of ζ dominate the S1 RRAM rather than the S3 RRAM. This variability control might be due to the interfacial engineering with the ultrathin Al2O3 dielectric layer, which will be discussed in detail in the Discussion part.

Figure 4

Statistical analysis of the TiO/Al2O3 bilayer RRAM. (a) Cycle-to-cycle and device-to-device distribution of the VSET the device. (b) Statistical distribution of ζ. Tight distribution is obtained with the S3 RRAM.

Variability and Endurance Dilemma

The performances of the S1, S2, and S3 devices are listed in Table . On the basis of the achievements, the performances are graphically represented in Figure a. The variability of three parameters, that is, forming voltage (VFORM), VSET, and ζ are plotted together. Figure S4 shows the surface plot of the overall variability. Ignoring the larger cycle-to-cycle or device-to-device nonuniformity in RS, the S1 RRAM is capable of showing good endurance cycles as compared to the S3 RRAM. Figure b shows the pulse test data of the cyclability of the S1 and S3 devices. A similar HRS degradation trend is followed by the S1 and S3 RRAMs. During the SET process of the S1 RRAM, the applied pulse was +5.5 V@500μs, and the RESET pulse was −3.0 V@10 ms. In the S1 RRAM, the continuous cycles increase the trapping probability of the TiO/Al2O3 stack. Although Al2O3 was deposited by the atomic-layer-deposition method, it still has some limitations in the performance. The continuous traps decrease the HRS value toward the LRS side. After 105 cycles of endurance, the HRS falls down rapidly. Because of the larger ζ of the S1 devices, at least a ζ of ∼5 can be achieved after 106 cycles of endurance.

Table 1

Variability Comparison of TiO/Al2O3 Bilayer RRAM Devicesa

			forming [V]		VSET [V]		HRS [MΩ]		LRS [MΩ]		ζ
Al2O3 [nm]		tunneling process	μ	σ	μ	σ	μ	σ	μ	σ	μ	σ
S1	8	CT + DT	13.9	2.7	5.4	0.92	19.46	4.701	1.16	0.457	21.62	7.35
S2	5	CT + DT	12.2	2.0	4.5	0.40	16.86	4.532	1.49	0.409	13.25	3.82
S3	2	CT	9.6	0.91	3.5	0.28	3.98	0.287	0.38	0.048	10.8	1.19

The ultrathin 2 nm Al2O3-based bilayer design shows the best uniformity control over the thicker devices.

Figure 5

Variability and endurance dilemma in the TiO/Al2O3 RRAM. (a) Variability plot with different RRAM structures. (b) Endurance test shows better cyclability of the S1 as compared to the S3 RRAM. (c) Uniformity and endurance dilemma. Thicker Al2O3 shows better endurance, and thinner Al2O3 shows excellent uniformity of RS.

During the SET process of the S3 RRAM, the applied pulse was +3.0 V@500μs and the RESET pulse was −3.0 V—10 ms. The LRS is very much controlled by the Al2O3 barrier layer thickness.[20] In this case, the LRS for the S3 is lower than that for the S1. In the S3 RRAM, the CT of the high energetic charge carriers damages the quality of the film and makes them leakier. The quick degradation of the HRS can be observed after 104 cycles. Therefore, a clear dilemma between endurance and switching uniformity is obtained as a function of the Al2O3 thickness which is illustrated in Figure c. The thicker Al2O3 RRAM improves the endurance capability, while switching uniformity is greatly enhanced by the ultrathin Al2O3 interfacial layer. Nevertheless, the endurance of the S3 devices can be further improved by inserting another thin Ti layer at the Al2O3/BL interface, the details of which will be discussed in our next report.

Discussion

The basic structure of S1, S2, and S3 RRAMs consists of similar materials. The difference is only in the thicknesses of the Al2O3 layer. The band gap φband, electron affinity χ, and dielectric constant ε of TiO2 are ∼3.2 eV, 4.2 eV, and 80, respectively; and for Al2O3, they are ∼8.8 eV, 1.25 eV, and 9, respectively. The Gibbs free energies ΔG of TiO2 and Al2O3 are −889.1 and −1582.3 kJ/mol, respectively. The work function (φmetal) values of TiN and IrO are 4.5 and 5.2 eV, respectively. Figure a,d,g shows the schematic structures of the S1, S2, and S3 devices, respectively. No such peculiarities were found in the forming behavior of the three types of RRAM devices. The VFORM decreases with decreasing thicknesses of the Al2O3 layer. In the VCM-type devices, it is well-expected that the VOs play a major role in controlling the CNF. Because of the lack of oxygen species in the atomic-layer-deposited Al2O3, higher energy is necessary to generate a sufficient number of VO to form the CNF. Therefore, the initial VFORM is large for the designed RRAM devices, and the forming process is abrupt rather than gradual. The ΔG suggests that the generation of VO is much difficult in Al2O3 as compared to the TiO layer; hence, the thicker Al2O3-based S1 RRAM needs higher voltage as compared to the thinner S3 devices. In addition, the applied voltage on the BL suggests that the generation of VO is not so easy, as the BL is not an oxygen-scavenging electrode. Hence, the generation and migration of VO is completely dependent on the structure design and can be controlled with the applied bias. Another aspect of this interfacial band engineering with an ultrathin Al2O3 layer is that it enhances the controllability of the formation and rupture process of the CNF. During the RS operation, the positive bias on the BL attracts the oxygen ions toward the top and hence the generation of the CNF. It is easier to form VO in the TiO layer than in the Al2O3 layer. As a result, a CNF based on VO migration forms in the reverse direction to the applied electric field E, that is, from the WL to the BL. The density of VO decreases from the TiO to Al2O3 side. In our previous report, we show that the metal–insulator–transition process can be realized in the 8 nm thick TiO film under the higher compliance current of ∼500 μA.[10] Here, we argue that at the 100 μA current level, instead of the formation of a Magneli phase filament, a locally enhanced VO-rich CNF is liable to perform the SET operation. Below a critical density to form the Magneli phase filament, the VO defect formation is expected over the whole TiO volume.[33,34] Because of the higher VO density, the connectivity in the TiO side is more stable than in the Al2O3 side. To RESET the device, a negative voltage was applied to the BL. With the applied negative bias, the oxygen ions repelled back to the structure to rescue their positions in the lattice site by capturing the VO defects. This process leads to the rupture of the CNF and switches the device from the LRS to the HRS. The rupture of the CNF is more likely to occur in Al2O3 because of the less amount of VO defect density. To explore the conduction mechanism, the experimental data of the devices were fitted with the theoretical data. The LRS of the S1 RRAM was fitted nicely with the trap-assisted tunneling (TAT) model at a voltage lower than 3 V, as shown in Figure S5a. Because of the applied bias, discrete trap sites will be created in the switching stack, and the charge conduction becomes possible by the trap-to-trap tunneling process.[35,36] The higher voltage range is fitted to the Fowler–Nordheim (F–N) tunneling model, as shown in Figure S5b. The tunneling phenomenon is always assisted by E. High E can decrease the width of the triangular barrier, and the charge carriers can tunnel easily. The carrier conduction by F–N tunneling is a general phenomenon of the flash memory devices.[37,38] In the RRAM, it is one of the conduction process reported by several studies.[39,40] Although the tunneling phenomenon starts at 1 MV/cm, the F–N tunneling probability always dominates at the higher E > 10 MV/cm.[41] The thickness of the modified Al2O3 tunnel barrier (TBmodified) at higher E can be approximated by the following equation

Figure 6

Schematic model for RS in the RRAM with variable Al2O3 thicknesses. (a–c) With the applied positive bias, oxygen ions move toward the BL to SET the device, and RESET is possible with the negative bias. For the S1 devices, the VO distribution for a fully grown and broken VO CNF is shown. (d–f) The similar behavior is picturized for S2 devices. (g–i) Mechanism for S3 devices. The ultrathin Al2O3 layer at the TiO/BL interface acts as a tunnel barrier.

Considering E ≈ 10 MV/cm and the F–N tunneling at the lowest voltage of 2.7 V (Figure S5b), the approximated TBmodified thickness of Al2O3 in the S1 RRAM is found to be <2.5 nm. Therefore, as shown in Figure S5c, the changes from high E to low E change the conduction mechanism from F–N tunneling to TAT.

When the voltage is applied to the BL, the VO-defect sites are generated and the charge carriers are transported through the traps by the trap-to-trap tunneling process. Incomplete filament formation is very much related to the tunneling model. In the TiO/Al2O3 structure, it is likely that there are more VO-defect sites in TiO rather than in Al2O3. Therefore, during RESET, the cell switching from the LRS to the HRS, a few oxygen ions can break the CNF in the Al2O3 side rather than in the TiO side. The cycle-to-cycle HRS to LRS switching indicates multiple breaks in the CNF. The breaking points and numbers are varied with cycles. Hence, the cycle-to-cycle rupturing processes of the CNF are nonuniform, but it is more likely to happen in the Al2O3 layer only. The situation is schematically illustrated in Figure b. The broken parts of the CNF provide an acting potential barrier for the carrier transmission process. On the basis of the evolution of the CNF, the reliability of the RRAM devices can be changed.[42] In our previous study, we have shown that tunnel resistance is very much related to the gap length (δ).[43] Considering three resistance changes of Figure a, the zoom-in view of the broken VO-CNF with three tunnel gaps (δ1 ≠ δ2 ≠ δ3) is illustrated in Figure c. Before approaching any gap, the current continuously increases with voltage, indicating a CT effect. The gap region is dominated by the DT process. For the 5 nm thick Al2O3 layer in the S2 RRAM structure, the probability of broken places is less than in the S1 structure. On the basis of the experimental data, the schematic illustration of the CNF in the S2 RRAM with one broken place is shown in Figure e. The experimental R–V nature of the inset of Figure c is illustrated in Figure f. The conduction follows the fashion similar to the S1 RRAM, that is, CT followed by DT. However, DT in the S2 devices is less than in the S1 devices.

When it comes to the S3 RRAM, no such DT was observed. In this case, the ultrathin 2 nm Al2O3 layer acts as the tunnel barrier layer, as shown in Figure g. This can enhance the nonlinearity in the TiO/Al2O3 RRAM.[8] The LRS conduction of the devices is fitted perfectly with the F–N tunneling model, as shown in Figure S5b. Because of the higher E, the electrons are able to tunnel through the triangular potential barrier of Al2O3 and hence conduction. Unlike the 8 nm thick S1 devices, the F–N tunneling mechanism is dominated by a comparatively lower voltage because of the ultrathin Al2O3 layer in S3 devices, which is another evidence of the scaling of the interfacial layer thicknesses in TiO/Al2O3-based RRAM devices. Figure h,i shows SET and RESET processes, respectively. In this process, there is no probability of the broken CNF in the Al2O3 layer. The suppression of the oxygen-scavenging effect mainly follows the thicknesses of the Al2O3 layer. The thicker the Al2O3, the larger the asymmetry in VO-defect density, creating more fluctuation in the RS process. Hence, the variability is greatly affected with the thickness scaling of the Al2O3 layer.

Meanwhile, the S1 RRAM shows higher endurance cycles than the S3 RRAM, as indicated in Figure c. However, HRS degradation dominates in both cases. The results suggest that the number of trap sites increases with the number of cycles, which degrades the quality of the TiO/Al2O3 bilayer stack with increasing cycles. The thicker film of the S1 devices has a better sufferance and trapping ability as compared to the S3 devices and hence the better endurance. However, the endurance of the S3 RRAM can be improved further by inserting a thin Ti layer in the Al2O3/BL interface, which will be discussed in our next report.

Conclusions

In summary, we have demonstrated the variability improvement in RS operation and cyclability in the TiO/Al2O3 bilayer RRAM devices by interfacial band engineering with an ultrathin ∼2 nm Al2O3 dielectric material, over the thick ∼8 nm Al2O3. The thicker film acts as a part of the RS switching layer, but the thinner film behaves as a tunnel barrier layer. At low field, the LRS conduction for the thick Al2O3 RRAM follows the TAT conduction and that for the tunnel barrier Al2O3 RRAM follows the F–N tunneling conduction model. The improvement has been achieved in the variation control in device forming, SET voltage distribution, HRS, LRS, and resistance ratio, with the ultrathin Al2O3-based TiO/Al2O3 bilayer RRAM devices.

Experimental Section

The 0.24 μm2 RRAM devices consist of the TiN/TiO/Al2O3/IrO structure. The TiN layer is the WL and IrO is the BL. The TiO/Al2O3 bilayer is placed at each junction point of the WL and the BL. The TiO layer with a thickness of 8 nm grew on the top of the WL with an oxidation plasma treatment. In between TiO and the BL, the Al2O3 layer grew by the atomic-layer-deposition technique with a thickness variation from 8 nm to a scaled one to 2 nm. The process steps are as follows: 200 sccm TMA@100ms → N2 purge@5s → 200 sccm TMA@100ms → N2 purge@5s → 150 sccm H2O@100ms → N2 purge@5s → 150 sccm H2O@100ms → N2 purge@5s. In total, 24 cycles, 60 cycles, and 96 cycles have done a 2, 5, and 8 nm thick Al2O3 layers. During the electrical measurements, all voltages applied on BLs and WLs were kept grounded.