| Literature DB >> 31336590 |
Jaechan Cho1, Yongchul Jung1, Dong-Sun Kim2, Seongjoo Lee3, Yunho Jung4.
Abstract
Most approaches for moving object detection (MOD) based on computer vision are limited to stationary camera environments. In advanced driver assistance systems (ADAS), however, ego-motion is added to image frames owing to the use of a moving camera. This results in mixed motion in the image frames and makes it difficult to classify target objects and background. In this paper, we propose an efficient MOD algorithm that can cope with moving camera environments. In addition, we present a hardware design and implementation results for the real-time processing of the proposed algorithm. The proposed moving object detector was designed using hardware description language (HDL) and its real-time performance was evaluated using an FPGA based test system. Experimental results demonstrate that our design achieves better detection performance than existing MOD systems. The proposed moving object detector was implemented with 13.2K logic slices, 104 DSP48s, and 163 BRAM and can support real-time processing of 30 fps at an operating frequency of 200 MHz.Entities:
Keywords: ADAS; FPGA; background subtraction; moving object detection; optical flow estimation
Year: 2019 PMID: 31336590 PMCID: PMC6679522 DOI: 10.3390/s19143217
Source DB: PubMed Journal: Sensors (Basel) ISSN: 1424-8220 Impact factor: 3.576
Figure 1Overall scheme of the proposed moving object detection (MOD) algorithm.
Figure 2Compensation for the integer parts of the ego-motion. The shaded region denotes empty space generated by the shift operation: (a) memory; (b) memory; (c) memory.
Figure 3Block diagram of the proposed moving object detector.
Figure 4Hardware structure: (a) optical flow estimator; (b) convolution calculator.
Figure 5Block diagram of the resolution process unit.
Figure 6Hardware structure of the camera motion estimator.
Figure 7Block diagram of the background detector.
Figure 8Block diagram of the object detector.
Implementation results for the proposed moving object detector.
| Block | FPGA Logic Slices (/51840) | DSP48s (/192) | Block RAM (/972) |
|---|---|---|---|
| Optical flow estimator | 12,312 | 96 | 108 |
| Camera motion estimator | 326 | 1 | 0 |
| Background detector | 443 | 5 | 50 |
| Object detector | 164 | 2 | 5 |
| Total | 13,245 (25.55%) | 104 (54.16%) | 163 (16.77%) |
Comparison of the proposed GMM-based background generator and previous research results.
| Target FPGA | Circuit | LUT | Slice | DSP48s |
|---|---|---|---|---|
| Virtex5 | Proposed | 729 | 325 | 3 |
| [ | 1066 | 346 | 10 | |
| [ | 724 | 323 | 3 | |
| Virtex6 | Proposed | 794 | 352 | 3 |
| [ | 788 | 349 | 3 |
Comparison of the processing speed of our approach with other work.
| Image Size | Processing Speed (fps) | |
|---|---|---|
| Fast MOD [ | Proposed | |
| 480 × 704 | 14.8 | 27.2 |
| 368 × 580 | 22.7 | 43.1 |
| 340 × 570 | 24.6 | 47.5 |
| 240 × 320 | 51.2 | 119.3 |
Figure 9FPGA test platform: (a) test environment; (b) Xilinx Virtex-5 FPGA based evaluation board; (c) 640 × 480 resolution camera.
MOD performance comparison between the proposed moving object detector and other algorithms.
| Algorithm | Precision | Recall | F-Measure |
|---|---|---|---|
| Rank-constrained 1 [ | 0.95 | 0.92 | 0.9348 |
| Rank-constrained 2 [ | 0.83 | 0.99 | 0.9030 |
| Kim et al. [ | 0.98 | 0.78 | 0.8686 |
| Proposed | 0.98 | 0.95 | 0.9648 |
Figure 10MOD performance of the proposed moving object detector.