Border Trap Extraction with Capacitance- Equivalent Thickness to Reflect the Quantum Mechanical Effect on Atomic Layer Deposition High-k/In0.53Ga0.47As on 300-mm Si Substrate.

This study presents a model to calculate the border trap density (Nbt) of atomic layer deposition high-k onto In0.53Ga0.47As on a 300-mm (001) Si substrate. This model considers the quantum confinement effect and band nonparabolicity. Capacitance-equivalent thickness (CET) was used to reflect the distance of the charge centroid from the oxide-semiconductor interface. The border trap values based on CET were found to be approximately 65% lower than the extracted values based on physical thickness in the In0.53Ga0.47As material. In an investigation of two different post-metal annealing effects on border traps, the border trap was more effectively passivated by N2-based forming gas annealing (FGA) compared with rapid thermal annealing (RTA), whereas a lower interface state density was observed in RTA-annealed samples compared with FGA-annealed samples. Nbt extraction at different bias voltages demonstrated that the applied frequencies travel deep into the oxide and interact with more traps as more the Fermi level passes the conduction band, thus creating tunneling with the carriers.

Introduction

As a substitute for conventional SiO2/n-type Si metal-oxide-semiconductor field-effect-transistors (MOSFETs), the combination of different higher dielectric constant (k) oxides along with InxGa1−xAs (x > 0.5) as a channel material has been extensively investigated for its potential equivalent oxide thickness (EOT) scaling and use in forthcoming logic-applicable devices that will require high-speed and depressed power consumption[1-5]. Among the different high dielectric constant (k) oxides, studies on Al2O3, HfO2, La2O3, ZrO2, and their nanolaminate and nano-mixture structures have already been reported[6-11].

In0.53Ga0.47As is often used instead of silicon because of its high electron mobility, which results from its lower effective mass of electrons. However, because of this lower effective mass of electrons, In0.53Ga0.47As suffers from low density of states (DOS)[12]. To be more precise, the DOS of In0.53Ga0.47As is less than that of Si by approximately two order of magnitudes[13,14]. As a result, this insufficient DOS causes the Fermi level of In0.53Ga0.47As to move inside the conduction band; otherwise, the benefit of its high mobility would be lost[4]. The band offset of high-k and In0.53Ga0.47As substrate is comparatively smaller than that of a conventional SiO2/Si interface.

Once the fermi level, E, has biased near the conduction band, the effective barrier height between the oxide and In0.53Ga0.47As, which is denoted as E − E, is reduced. As a result, the trap inside the oxide starts the charge/discharge process with electrons from the semiconductor through tunneling[14]. These traps, which are positioned in the dielectric near the oxide–In0.53Ga0.47As interface, are commonly known as border traps[15-17]. The idea of these traps was first introduced by Fleetwood[15]. Border traps are characterized by their location: the farther they are from the interface, the longer it takes for the majority carrier to fill them. Their charge exchange is also determined by the applied alternating current (ac) frequency. A lower frequency provides deep tunneling by decreasing the apparent thickness of the oxide, whereas the tunneling probability decreases at a higher frequency[16].

Figure 1a shows how the tunneling of electrons occurs from the semiconductor to oxide layer in response to an applied AC frequency with sufficient direct current (DC) bias voltage. However, the effect of these near-interfacial dielectric traps is a great stimulus for the on-state act of a MOSFET. Because the fermi level (E) is pinned inside the conduction band, border traps prevent the formation of sufficient carriers in the channel, which leads to reduced carrier mobility by phonon scattering and eccentricity of the threshold voltage[17,18]. These traps are also responsible for reduction of gate voltage control on the channel current, enhancing gate leakage current, a degradation of transconductance as well as for hysteresis[19,20]. The impact of border traps is more prominent in the accumulation region, where a dispersion is always observed in the capacitance-voltage (C-V) response of the metal-oxide-semiconductor (MOS) capacitor because of the transportable carrier exchange among the border traps and conduction band states via tunneling, as described previously[21-24].

Figure 1

(a) Energy-band diagram of a metal/Al2O3/n-InGaAs MOS capacitor with the interface and border traps when an AC signal is applied. (b) Response regions of the interface and border traps in the capacitance-voltage (C-V) behavior of the Al2O3/n-InGaAs MOS capacitor. (c) Equivalent circuit diagram for the gate capacitance of the III–V MOSFET.

Figure 1b illustrates the region where border traps are prominent as an active trap state in capacitance-voltage (C-V) with a frequency dependency from 10 kHz to 1 MHz. Unlikely, the typical interface state model cannot explain this dispersion because the time constant of these traps at accumulation is much smaller than that of the bulk oxide traps, within the typical measurement frequency range from 1 kHz to 1 MHz[25]. The electrical behavior of border traps is quite different from that of interface traps in several ways. Firstly, the interface traps are inactive at the energy value of the accumulation region, where the frequency scattering occurs[22]. Secondly, compared with the time constant that is responsible for the interface trap’s charging/discharging, the dispersion performance is less temperature dependent because of the border traps[26]. Finally, the chemical treatment has no effect on border traps but successfully diminishes the dispersion caused by interface traps[27].

Researchers have proposed several methods for modelling the dispersion of capacitance at accumulation and making electrical characterizations of border traps[22-25,28-31]. Among them, the distributed border trap model from Yuan et al. is the most well known[28,31]. In this model, the oxide thickness (t) is segregated into immeasurable quantities of small fragments, with each part contributing an amount of oxide capacitance, ΔC, connected in parallel with the admittance proportional to the border trap density; this parallel combination is connected in series with the semiconductor capacitance. The border trap density is then extracted by making a best-fit condition between the calculated capacitance and the conductance achieved from this model and experimental values. Usually, this oxide thickness is mainly the physical thickness (t) or EOT, which is the result of either ellipsometry or transmission electron microscopy analysis.

When determining the semiconductor capacitance C, it is not clear that previous studies’ consideration about the quantum mechanical effect[12,25,32-34]. For practical purposes, this capacitance is not only the oxide capacitance but also a series combination of inversion capacitance (C), which includes quantum capacitance (C) and centroid capacitance (C), by assuming that the first electron sub-band in the channel is occupied[35,36]. Therefore, the total capacitance includes a series combination of insulator capacitance (C), quantum capacitance (C), and centroid capacitance (C). The equivalent electrical circuit is shown in Fig. 1c. In a large-scale device, the series combination of C and C is larger than C, so the gate capacitance approaches only C. However, in small-scale devices, the oxide thickness is on a nanometer scale; thus, C becomes commensurate with the other components of total capacitance[35].

Quantum capacitance (C), which is proportional to the DOS of the channel material, physically originates from the Fermi-level penetration onto the conduction band. In the III–V channel material, a two-dimensional electron gas requires energy to be created in the semiconductor quantum well region because of low density-of-states (DOS). Therefore, the Fermi level moves above the conduction band to increase the charge in the quantum well. This movement requires energy and conceptually is equivalent to quantum capacitance. However, charges in the quantum well take a bell-shaped distribution rather than distributing themselves in a sheet form with zero thickness, which means that the physical distance of each charge is quite different from the metal gate. Moreover, the center of the charge distribution may be away from the insulator–semiconductor interface due to the confinement in the quantum well. These effects should be considered when modelling the total capacitance. When these factors are excluded, the overall capacitance is overestimated, so the extracted border trap density (N) is inaccurate[32]. To improve the extraction of border trap density, total semiconductor capacitance (C) should be included with the quantum confinement effect and band nonparabolicity in the model. Additionally, because of the quantum mechanical confinement consequence of the carriers, the supplementary thickness of the conductive channel should be considered because the charge centroid in the conductive channel is located deeper beneath the interface of the dielectric and semiconductor, as described previously[37].

Capacitance-equivalent thickness (CET) reflects a more realistic set-up because it considers the above-mentioned effect. Therefore, border trap extraction using a CET metric is a more reliable way to obtain the accurate density of border traps. In this study, we used the CET metric for the extraction of N in addition to using physical thickness and determined that border trap density is overestimated when the quantum mechanical effect is not considered. In addition, because a border trap is an oxide’s native property, the parameters of oxide growth from atomic layer deposition (ALD) must have some effects on border trap formation. In this regard, we also examined the effects of ALD growth temperature on border traps. Moreover, several studies have passivated border traps using a variety of annealing processes[33,38]. Thus, we also examined the passivating effects of two types of annealing processes on border traps. Lastly, the interface trap density (Dit) was also extracted for samples that were differentiated with the passivation scheme.

Model Description

Gate capacitance model

The total capacitance of III–V MOS structures is modelled as a series combination of insulator capacitance (Cins) and inversion capacitance (Cinv) by assuming no doping level underneath the channel as demonstrated in Fig. 1c. It consists of a parallel combination of contributions of each occupied electron subband in the channel. From the figure it is evident that, for each subband i, the inversion-layer capacitance (Cinv_i) consists of the quantum capacitance (CQ_i) and the centroid capacitance (Ccent_i) which are connected in series. So, inversion-layer capacitance can be defined aswhere, ψ is the surface potential, EF is the fermi level, EC is the conduction band edge at the barrier-channel interface on the channel side, and Qs is the total electron charge in the channel which is the sum of all the charges in each of the sub bands. This can be formulated aswhere, Qi is the electron charge of subband i in the channel, Ei is the energy level of subband i, and is the in plane effective mass of the channel material. The effective mass is a function of energy due to nonparabolicity of the band structure which can be expressed as follows[39].where, is the effective mass at k = 0, E and k are the energy and wave number of the charge carrier, ħ is the reduced Plank’s constant and α is the nonparabolicity parameter.

Now, we can define quantum capacitance for any subband (CQ_i) as the derivative of electron charge in subband i with respect to energy difference between EF and Ei. Mathematically,

Similarly, centroid capacitance of subband i (Ccent_i) can be defined as the derivative of electron charge in subband i with respect to energy difference between Ei and EC.

Then Cinv_i can be formulated as

So, if the location of each subband energy level (Ei) and the fermi level (EF) are known with respect to conduction band edge, then all the capacitance component can be evaluated.

Border trap extraction model

For a quantitative analysis of border trap density, we followed the distributed border trap model as mentioned previously. This model enumerates the border traps by analyzing the frequency dispersion at an accumulation region at any specific bias voltages. The whole oxide capacitance is modelled onto an abundant number of small capacitive components, ΔC, where each component characterizes the capacitance of a very small piece of oxide thickness. The induced charge storage and energy loss from the border traps are modelled by a series of connected capacitance (ΔC) and conductance (ΔG) for any portion of oxide thickness. This admittance due to border traps is connected in parallel to the oxide capacitance. This parallel combination is then connected in series with the semiconductor capacitance. Figure 2 shows the equivalent electrical circuit of the model. The whole model can be described by a first-order non-linear ordinary differential equation, as follows:with the boundary condition at x = 0, Y = jωC where Y is the total admittance at any distance x from the oxide–semiconductor interface; ω = 2πf is the angular ac frequency, where f is the measurement frequency and C is the semiconductor capacitance corresponding to a specific surface potential ψ.

Figure 2

Equivalent electrical circuit representation of an MOS capacitor using the distributed bulk oxide trap model[28,31].

The other important parameters of this model are described as follows: q is the elementary electron charge in Coulombs; ε = ε · ε0 is the permittivity of any dielectric film, where ε is the relative permittivity of the oxide layer and ε0 is the permittivity of the air; C is the oxide capacitance per cm2, which is defined as ε/t, where t is the thickness of the oxide layer in centimeters; N is the volume concentration of border traps in the oxide at a distance x from the oxide–semiconductor interface at any energy level, expressed as eV−1 cm−3; and τ is the average time in seconds for electron capturing of an empty trap. τ maintains an exponential relationship with the distance x, which is the distance of the trap within the oxide from the interface. τ can be described as follows:Here, τ0 is the capture/emission time constant of the trap having the same energy level of τ. k is the attenuation coefficient of the tunneling process, which can be described by the effective mass of dielectric film (m*), the barrier height between the conduction band of oxide and semiconductor (E), and the reduced Plank’s constant (ħ). Moreover, τ0 can be described more specifically as:Here, v is the thermal velocity of any electron at any temperature T, n is the semiconductor surface’s electron density, and σ is the border trap’s capture cross-sectional area. As described elsewhere[13], at the accumulation region where the Fermi level is near the conduction band, a good approximation is to consider n as equal to the DOS (N) of the conduction band. Moreover, the border traps that are deeply inside of the oxide do not respond at any applied frequency ω having a time constant τ that is greater than 1/ω; however, the traps closer to the interface with a smaller τ are more willing to respond. Using the condition ωτ = 1, the probing depth at any applied frequency for a border trap can be calculated as follows:

Here, f is the measurement frequency.

Results and Discussion

Figure 3 shows the evolution of the sub-band energy levels and all capacitance component modelling, along with experimental data from an Al2O3 ALD-deposited sample. For our modelling, we solved the self-consistent solution of the one-dimensional Poisson and Schrodinger equations using the Nextnano simulation tool[40]. This tool provides the values of sub-band energy (E) and conduction band energy (E) with respect to the fermi level energy (E). The inset of Fig. 3 shows the evolution of the sub-band energy levels (E) with respect to the fermi level (E) at the applied bias voltage range. From the figure, it is evident that the fermi level penetrates the first and second energy levels while being very close to the third energy level. Thus, both the first and second sub-bands of the quantum well are populated by electrons in the operational voltage range.

Figure 3

Evolution of sub-band energy levels with respect to Fermi level (inset), experimental C, and modeled C components of an ALD-processed sample.

Figure 3 also illustrates the measured capacitance of rapid thermal annealing (RTA) and forming gas annealing (FGA)-processed samples with modelled gate capacitance and its components. The model extraction was done by considering the conduction band effective mass of In.53Ga.47As to be 0.043m0 (m0 = electron mass at rest) by considering a non-parabolicity effect as reported in literature[41] as well as optimizing other material parameters according to their physical structures[13]. The extracted gate capacitances were well harmonized with the modelled data. The insulator capacitance was calculated by considering the ideal dielectric constant (k), which is 9, and the measured oxide thickness. However, in the experimental cases, the gate capacitance approached approximately 63% of C for the RTA-processed sample. The same condition is also valid for FGA processed samples as depicted in the Fig. 3. This capacitance deprivation mostly results from the effects of inversion capacitance. As demonstrated, C is quite comparable with the insulator capacitance; in addition, C is more dominant than C because of the smaller effective mass of the In0.53Ga0.47As channel. It is also clear that the capacitance dominance of any sub-band energy depends on its electron population density. Therefore, C is much smaller than C and C is negligible according to the fermi level penetration into the sub-band, as shown in the inset of Fig. 3.

For the extraction of border traps, the parameters of “Eq. (7)” were executed as follows. The oxide capacitance was calculated by dividing the oxide permittivity by the oxide thickness. The oxide relative permittivity was calculated according to the formula in “Eq. (11)” for every case, using the maximum capacitance value at a frequency of 10 kHz from the measured C-V data. To calculate the attenuation coefficient, the electron effective mass in Al2O3 was considered to be 0.23 m0 based on the literature[33], where m0 is the electron mass at rest; in addition, the barrier height between the oxide and semiconductor conduction band edge was calculated using the electron affinity rule. The semiconductor capacitance C was taken at the extraction voltage of the border traps using a one-dimensional Poisson-Schrodinger solver simulation tool (Nextnano) by simultaneously considering quantum confinement and non-parabolic band effects[40]. CET was calculated according to “Eq. (12)” in the Methods section using the capacitance value from 100 kHz at the border trap extraction voltage. Both N and τ0 were used as fitting parameters to achieve the best-fit curve for capacitance from the model by solving “Eq. (7)” with the measured data. A list of parameters that were used for the modelling is presented in Table 1.

Table 1

Summary of parameters used for the extraction of border trap density.

Sample	RTA-Processed Samples			FGA-Processed Samples
Parameter	200 °C	250 °C	300 °C	200 °C	250 °C	300 °C
tox [nm]	4.2006	3.867	3.5128	4.2006	3.867	3.5128
CET [nm]	2.67	2.469	2.31	2.95	2.62	2.4
εr	6.93	6.71	6.26	5.87	6.24	6.07
m*	0.23	0.23	0.23	0.23	0.23	0.23
Eb [eV]	3.65	3.65	3.65	3.65	3.65	3.65
k [nm−1]	4.5	4.5	4.5	4.5	4.5	4.5
Cs [μF/cm2]	1.08	1.143	1.22	1.08	1.143	1.22
τ0 [s] (Using tox)	1 × 10−11	1 × 10−12	1 × 10−12	1 × 10−12	1 × 10−12	1 × 10−13
τ0 [s] (Using CET)	3 × 10−11	1 × 10−11	1 × 10−12	1 × 10−12	1 × 10−11	1 × 10−13
Nbt [cm−3 eV−1] (Using tox)	1.28 × 1020	1.1 × 1020	1 × 1020	9.6 × 1019	9.75 × 1019	7.6 × 1019
Nbt [cm−3 eV−1] (Using CET)	4 × 1019	4.1 × 1019	3.09 × 1019	2.98 × 1019	3.58 × 1019	2.72 × 1019

Figure 4 shows the N extraction fitting curves at 1 V using physical thickness t for both the RTA- and FGA-processed cases. In both cases, the samples deposited at 200 °C show the lowest capacitance compared with the 250 °C and 300 °C deposited samples. This variation in capacitance values is mainly due to the difference in thickness between the samples deposited at different temperatures. As mentioned previously, the 200 °C processed samples showed the greatest thickness and henceforth the lowest capacitive value. The opposite case was observed for the 300 °C deposited samples. In another interesting observation, the FGA-processed samples showed somewhat lower capacitance in three different deposition cases compared with their respective RTA-processed samples. However, in the RTA-processed samples shown in Fig. 4a, there was more distortion of capacitance at the lower frequencies of the measurement window (10 kHz to 1 MHz) than at the higher ones. This disturbance in capacitance may be attributed to the noise associated with lower frequency measurements[42]. On the contrary, the FGA-processed samples did not suffer from this limitation.

Figure 4

Model fitting of the capacitance versus frequency curves for the measured data (solid symbols) and calculated data from distributed border trap model (solid lines) using physical thickness (t) at an applied DC gate bias of 1 V. The fitting was performed for three different deposition conditions of Al2O3 on n-InGaAs. Shown here are the (a) RTA conditions and (b) FGA conditions.

In both cases at higher frequencies of the measurement window, the experimental data diverged from the fitting curve and displayed a different slope of capacitance versus log(ω). This change in the gradient of the capacitance versus log(ω) at higher frequencies is consistent at the measurement frequency range, which may be attributed to the distribution of border traps. A high concentration of traps (in the range of 1021 cm−3 eV−1) was reported at <1 nm from the oxide–semiconductor interface. Notably, this high density of traps that are positioned at <1 nm from the Al2O3/InGaAs interface are also found at the lower frequencies of measurement[33]. However, the extracted border trap densities of the 200 °C, 250 °C, and 300 °C deposited RTA samples were 1.28 × 1020 cm−3 eV−1, 1.1 × 1020 cm−3 eV−1 and 1 × 1020 cm−3 eV−1, respectively. For FGA samples, the extracted border trap densities were 9.6 × 1019 cm−3 eV−1, 9.75 × 1019 cm−3 eV−1 and 7.6x × 1019 cm−3 eV−1, respectively. The value of τ0 in these extractions was in the range of 10−12 s, which is attributed to the lower capture cross-sectional areas of the traps.

Figure 5 shows the N extraction for the same samples by considering the quantum mechanical effect. In this case, the physical thickness was replaced by the CET, and these CET values were extracted for all six cases. Both N and τ0 were used as fitting parameters as before, while keeping the other parameters unchanged. Both the disturbance in capacitance at lower frequencies and the distortion of the gradient of capacitance versus log(ω) also existed in this case. The simulated curves obtained from the model showed a better fit than previous cases. The N values extracted for RTA samples were 4 × 1019 cm−3 eV−1, 4.1 × 1019 cm−3 eV−1, and 3.09 × 1019 cm−3 eV−1 for the deposition conditions of 200 °C, 250 °C, and 300 °C, respectively. For the FGA samples, the N values were 2.98 × 1019 cm−3 eV−1, 3.58 × 1019 cm−3 eV−1, and 2.72 × 1019 cm−3 eV−1, respectively. τ0 was also in the same range as earlier. However, the N values extracted using CET were much lower than the values obtained by using physical thickness, t. This comparison is illustrated in Fig. 6a,b. The N values by CET were approximately one third of (~65% lower than) the values by t. The overestimation of N values using physical thickness may be because the additional thickness of the oxide layer due to quantum confinement in the In0.53Ga0.47As layer is not considered. Because the charge centroid is shifted, it causes the oxide–semiconductor interface to shift a finite thickness. As a result, the interface traps, which may contribute to energy loss, are excluded.

Figure 5

Model fitting of the capacitance versus frequency curves for the measured data (solid symbols) and calculated data (solid lines) as in Fig. 4 using capacitance-equivalent thickness (CET) at an applied DC gate bias of 1 V. Shown here are (a) RTA conditions and (b) FGA conditions.

Figure 6

Extracted border trap density (N) difference between the physical thickness (t) and capacitance-equivalent thickness (CET)-based extraction. The comparisons were made for all three deposition conditions. Shown here are (a) RTA conditions and (b) FGA conditions.

Figure 7a,b compare the extracted N values of both RTA- and FGA-processed samples at three different deposition temperatures, as described previously. In both cases, the FGA-processed samples showed lower values of N than did the RTA-treated samples. This indicates that defect passivation is more effective during the FGA process. In addition, more hydrogen (H2) is incorporated to passivate the dangling bonds, which is the reason for the border traps within the amorphous Al2O3 dielectric in the FGA process[38]. However, the RTA-processed samples showed comparatively lower D values than did the FGA-processed samples. Therefore, RTA treatment passivated the interface traps, whereas border traps are treated by FGA effectively. Furthermore, N was observed to be the lowest for the 300 °C deposited sample comparing with the 200 °C and 250 °C deposited samples for both RTA- and FGA-processed cases. This lower N indicates structural differences in the film stoichiometry at 300 °C, which leads to more hydrogen (H2) incorporation during FGA, as reported elsewhere[38]. Therefore, the probability of hydrogen (H2) bonding to defects is increased.

Figure 7

(a) Extracted border trap density (N) and (b) interface trap density (D) comparisons between two different annealing processes of Al2O3/n-InGaAs samples according to their different deposition temperatures.

Figure 8 shows the N spatial distribution as a function of gate voltage, as well as the distance of the probing depth from the interface into the oxide. The values of N were extracted at different applied DC voltages, whereas the values of τ0 were used to determine the probing depth into the oxide at any measurement frequency. Because border traps are more responsive at lower frequencies and the physical distance into the oxide up to where the traps respond is inversely proportional to the applied frequency, we used the lowest frequency of the measurement window (i.e., 10 kHz) to calculate the response region. The N distribution increases as the applied voltage is increased. With the applied voltage increase, the Fermi level penetration into the conduction band also increases; in addition, the effective barrier height decreases, which makes the majority of carriers more likely to tunnel into the deep traps. When the applied voltage increases, traps with smaller electron capture cross-sectional areas in the deep oxide layer respond. Because all parameters, excluding τ0, are the same at different extraction voltages, a smaller τ0 results in a larger tunneling distance.

Figure 8

Spatial distribution of border trap density (N) as a function of applied gate voltage, as well as the location in an Al2O3 dielectric from the Al2O3/n-InGaAs interface.

Conclusion

We extracted the border trap density of an Al2O3 oxide layer deposited at three different temperatures to n-In0.53Ga0.47As on a 300-mm Si substrate by considering the quantum mechanical effect. Because quantum confinement and charge centroid effects are more prominent in relatively small-scale devices, these effects must be considered to model N in the oxide layer.

We calculated the density of border traps using both physical thickness and CET while keeping other parameters constant. The N values extracted using CET were approximately 65% lower than N values obtained by physical thickness. The samples were also processed by different annealing treatments. FGA-annealed samples showed comparatively lower N values than did than RTA-processed samples, although the RTA-processed samples had lower D values. The FGA treatment helps to passivate the border traps, whereas the interface traps are passivated by RTA. Moreover, samples deposited at 300 °C showed moderately low border trap concentrations because of their different stoichiometric structure, which allowed for more H2 incorporation during FGA. The relationship between tunneling distance and border trap concentration with respect to border trap extraction voltage was also studied. With an increase of applied voltage as the Fermi level penetrated into the conduction band, the tunneling distance was observed to be deeper from the response of more traps with relatively small electron capture areas.

Methods

Sample preparation and measurements

An In0.53Ga0.47As n-type heterostructure was created by metal-organic chemical vapor deposition (MOCVD) according to the procedure described here. First, two strain-relaxation buffer epitaxies of GaAs and InP were grown on a typical 300-mm n-type Si (001) substrate following the Volmer-Weber growth mode, with a carrier concentration of 2 × 1018 cm−3 on each layer and thicknesses of 350 nm and 800 nm, respectively. Then, an upper structure was formed, which consisted of a 110-nm Si-doped n-In0.53Ga0.47As layer with an electron density of 5 × 1017 cm−3 as the bottom layer and another 160-nm Si-doped n-In0.53Ga0.47As layer with an electron density of 1 × 1017 cm−3 as the upper layer.

A total of six samples of ALD Al2O3 with a configuration of 30 cycles on In0.53Ga0.47As were prepared. They were deposited at three different growth temperatures of 200 °C, 250 °C, and 300 °C, while two samples were arranged at any specific temperature. Prior to deposition of the dielectric, the In0.53Ga0.47As substrates were treated with several wet cleaning processes to remove any native oxide or other contaminants. At the start, the substrates were cleaned with acetone and isopropyl alcohol for 5 minutes each. Then, they were treated with a solution of diluted hydrochloric acid (HCl) and deionized (DI) water, maintaining a ratio of 1:10 at room temperature for 30 s to eliminate any native oxide. Subsequently, they were cleaned with deionized water for 2 minutes and dried in a nitrogen (N2) environment to displace the water from the wafer surface so that no water mask could form.

After the solution treatment, the substrates were transported to an ALD chamber within a minimal time interval. Before starting the actual deposition, 10 cycles of trimethylaluminium (TMA) preclean were performed because it was reported to be beneficial for passivating the interface trap density due to a self-cleaning effect[20,42,43]. Then, the Al2O3 dielectric was deposited by ALD using TMA and water (H2O) as the metal precursor and oxidant, respectively. The deposition process began with a TMA pulse onto the In0.53Ga0.47As surface and then was followed with a water pulse. The pulse time was 0.1 s in both cases. Between the TMA pulse and water pulse, a purge duration of 20 s was maintained. Nitrogen (N2) was used for both the purge and carrier gas, with a flow rate of 300 sccm. Both the TMA and water reservoirs were at room temperature.

The physical thickness (t) of the ALD-deposited Al2O3 layers was quantified by ellipsometry at an incident angle of 70°. The thicknesses were found to be 4.2006 nm, 3.867 nm, and 3.5128 nm for the 200 °C, 250 °C, and 300 °C deposition cases, respectively. Therefore, for MOS capacitor formation after Al2O3 deposition, an ALD 5-nm TiN layer was deposited on top of the dielectric. Then, a metal layer of Ti/Au (200/2000 Å) was deposited by electron-beam (E-beam) evaporation for frontside metal contact by a lift-off process. The same metal layer was again deposited for backside metal contact. Reactive-ion etching based on SF6/Ar Gas (30/10 sccm) was used to etch the TiN layer.

After the MOS capacitor formation, one set of samples deposited at three different temperatures was processed by RTA for 2 minutes at 350 °C in nitrogen (N2) ambient, whereas another set was annealed at 300 °C in forming gas (N2:H2 = 96%:4%) for 30 minutes. The C-V curves at a frequency range from 10 kHz to 1 MHz were measured at room temperature using a Keithley 4200A-SCS parameter analyzer by applying a gate voltage. The effective relative permittivity (ε) and CET were calculated according to the following equations:Here, C is the maximum capacitance per unit area and t is the oxide thickness.Here, C is the accumulation capacitance per unit area. The interface trap density (D) was calculated through the conductance method by measuring the parallel conductance (G/ω)[44].