| Literature DB >> 31131198 |
Qilin Hua1, Huaqiang Wu1, Bin Gao1, Meiran Zhao1, Yujia Li1, Xinyi Li1, Xiang Hou2, Meng-Fan Marvin Chang3, Peng Zhou2, He Qian1.
Abstract
Leakage interference between memory cells is the primary obstacle for enlarging X-point memory arrays. Metal-filament threshold switches, possessing excellent selectivity and low leakage current, are developed in series with memory cells to reduce sneak path current and lower power consumption. However, these selectors typically have limited on-state currents (≤10 µA), which are insufficient for memory RESET operations. Here, a strategy is proposed to achieve sufficiently large RESET current (≈2.3 mA) by introducing highly ordered Ag nanodots to the threshold switch. Compared to the Ag thin film case, Ag nanodots as active electrode could avoid excessive Ag atoms migration into solid electrolyte during operations, which causes stable conductive filament growth. Furthermore, Ag nanodots with rapid thermal processing contribute to forming multiple weak Ag filaments at a lower voltage and then spontaneous rupture as the applied voltage reduced, according to quantized conductance and simulation analysis. Impressively, the Ag nanodots based threshold switch, which is bidirectional and truly electroforming-free, demonstrates extremely high selectivity >109, ultralow leakage current <1 pA, very steep slope of 0.65 mV dec-1, and good thermal stability up to 200 °C, and further represents significant suppression of leakage currents and excellent performances for SET/RESET operations in the one-selector-one-resistor configuration.Entities:
Keywords: Ag nanodots; cross‐point; one‐selector‐one‐resistor (1S1R); selectors; threshold switch
Year: 2019 PMID: 31131198 PMCID: PMC6524079 DOI: 10.1002/advs.201900024
Source DB: PubMed Journal: Adv Sci (Weinh) ISSN: 2198-3844 Impact factor: 16.806
Figure 1Cross‐point (X‐point) memory in one‐selector‐one‐resistor (1S1R) configuration. a) Schematic illustration of sneak current in 2D X‐point memory cells during read operation. “0” stands for off‐state, while “1” stands for on‐state. b) Schematic illustration of 3D X‐point memory with integration of ordered Ag nanodots based threshold switch (AND‐TS) and memory in 1S1R configuration. Red circle is the AND‐TS stack schematic of ordered Ag nanodots/HfO2 based selector. c) Repeated cycling I–V characteristics of TaO/Ta2O5− bilayer RRAM. The inset shows SEM image of X‐point RRAM (left) and schematic illustration of RRAM stack structure (right). Scale bar: 100 µm. d) I–V characteristic of AND‐TS in X‐point structure. e) I–V characteristics of 1S1R integrated device in 50 DC voltage sweep cycles, exhibiting ultralow leakage currents (≈pA) at low voltages. The RESET currents (I RESET) are larger than 1 mA (maximal I RESET ≈ 2.3 mA). The inset is schematic illustration of the 1S1R device stack structure.
Figure 2Device fabrication process and morphology characterization. a) Schematic illustration of AND‐TS fabrication process. b–e) SEM images of Ag nanodots morphology in the process (scale bar: 200 nm). b) Ordered Ag nanodots (left) fabricated through ultrathin AAO template (right). c) Enlarged SEM image of Ag nanodots before rapid thermal processing (RTP) treatment. d) SEM image of ordered Ag nanodots after RTP treatment. e) Enlarged SEM image of Ag nanodots after RTP treatment. f) STEM image of RTP‐treated Ag nanodot/HfO2 device stack layers, and the corresponding fast Fourier transform (FFT) patterns of g) Ag and h) HfO2.
Figure 3Excellent selector performance of AND‐TS. a) Threshold switching behavior of AND‐TS at different compliance current (I cc) from 100 nA to 1 mA, showing extremely high selectivity (on/off ratio) over 109. b) Read resistance following turn‐on operation at increasing compliance currents for TS devices with RTP‐treated Ag nanodots (top) and Ag thin film (bottom) as active electrode. The device with RTP‐treated Ag nanodots (known as AND‐TS) can improve on‐state current up to 1 mA. c) Bidirectional threshold switching behavior of AND‐TS in 50 DC voltage sweep cycles. d) Cumulative probability of turn‐on voltage (threshold voltage, V th) as cycle‐to‐cycle (left) and device‐to‐device (right). e) AND‐TS has an extremely small turn‐on/turn‐off switching slope of <1 mV dec−1 (turn‐on: 0.66 mV dec−1; turn‐off: 0.65 mV dec−1). f) Thermal stability of AND‐TS at elevated temperatures. AND‐TS can still have high reliable current changes in large on/off ratio (>108, under current compliance) although its work temperature varies from 25 to 200 °C.
Figure 4Mechanism of AND‐TS. a) Simulation for the formation of multiple weak Ag filaments with applied voltage (V a = 0.4 V). b) Simulation for the corresponding conductive paths of multiple weak Ag filaments in normalized current. c) Conductance quantization characteristics of the AND‐TS device in experiment (forward voltage sweep: blue; reverse voltage sweep: red) and simulation (black) results. d–g) Schematic illustration for the mechanism of AND‐TS based on Ag filament formation/rupture under different voltage bias. h) HAADF‐STEM cross‐sectional image of AND‐TS stack layers. i–l) Energy‐dispersive X‐ray spectroscopy (EDS) mapping of Ag, Hf, O, and Pt elements in the device stack layers, respectively, after one‐time positive voltage sweeping.
Figure 51S1R configuration in X‐point devices. a) Schematic illustration for 1S1R integration with resistive memory (TaO/Ta2O5− ) and AND‐TS. b) I–V characteristics of the integrated 1S1R device before and after 108 cycles. c) Excellent endurance during over 108 pulse measurement for 1S1R configuration. The waveform employed in the endurance measurement which consists of 10 µs pulses with amplitudes of ±2 V for RESET/SET operations, and the time interval between switching pulses is 40 µs. The read operations are conducted by applying two voltage biases (0.15 and 0.3 V) simultaneously after a certain number of pulses testing.