ALD-Zn xTi yO as Window Layer in Cu(In,Ga)Se2 Solar Cells.

We report on the application of Zn xTi yO deposited by atomic layer deposition (ALD) as buffer layer in thin film Cu(In,Ga)Se2 (CIGS) solar cells to improve the photovoltaic device performance. State-of-the-art CIGS devices employ a CdS/ZnO layer stack sandwiched between the absorber layer and the front contact. Replacing the sputter deposited ZnO with ALD-Zn xTi yO allowed a reduction of the CdS layer thickness without adversely affecting open-circuit voltage ( VOC). This leads to an increased photocurrent density with a device efficiency of up to 20.8% by minimizing the parasitic absorption losses commonly observed for CdS. ALD was chosen as method to deposit homogeneous layers of Zn xTi yO with varying Ti content with a [Ti]/([Ti] + [Zn]) atomic fraction up to ∼0.35 at a relatively low temperature of 373 K. The Ti content influenced the absorption behavior of the Zn xTi yO layer by increasing the optical bandgap >3.5 eV in the investigated range. Temperature-dependent current-voltage ( I- V) measurements of solar cells were performed to investigate the photocurrent blocking behavior observed for high Ti content. Possible conduction band discontinuities introduced by Zn xTi yO are discussed based on X-ray photoelectron spectroscopy (XPS) measurements.

Introduction

Photovoltaic devices (PV) based on a chalcopyrite Cu(In,Ga)Se2 (CIGS) absorber layer are among the most promising thin-film PV technologies with laboratory scale power conversion efficiencies (PCE) exceeding 20% on a flexible polymer substrate and 22.9% on a soda lime glass (SLG) substrate.[1,2] These champion device efficiencies were achieved with a chemical bath deposited (CBD) CdS buffer. The relatively low band gap energy of CdS (2.4–2.5 eV) leads to a parasitic absorption in the short wavelength region since light absorbed by CdS does not contribute to the photocurrent which limits the optimum device performance.[3]

Alternative buffer/window layers such as Zn(S,O), ZnMgO, InS, ZnSnO, and ZnTiO have been applied in CIGS devices due to their wider bandgap or lower absorption coefficient achieving PCEs of 21.0%, 20%, 18.2%, 18.2%, and 12.5%, respectively.[4−8] With the introduction of heavy alkali (KF, RbF) post-deposition treatments (PDT) on CIGS absorbers the minimal thickness of CdS required for optimal PV performance was reduced from 50 nm to about 30 nm.[1,9,10] Thinner (<30 nm) CdS layer can lead to nonuniform coverage of the CIGS surface that would leave it prone to sputter damage during the subsequent ZnO/Al:ZnO window layer deposition.[11,12] Furthermore, a possible cliff like band alignment at the CIGS/ZnO interface leads to carrier recombination degrading the I–V parameters VOC and fill factor (FF).[13,14] To mitigate sputtering damage, plasma-free methods for the deposition of metal oxide window layers have been investigated: B:ZnO Al2O3, ZnTiO, or TiO2 were deposited by either metal–organic chemical vapor deposition (MOCVD) or ALD.[8,11,12,15]

In our previous report,[11] ALD-TiO2 has been applied as highly transparent and resistive (HTR) window layer replacing sputtered ZnO (sp-ZnO) in its function of preventing electrical inhomogeneities and shunt paths.[16,17] In this case, VOC showed to be less affected by the CdS thickness and the optimum device performance was achieved with a 10 nm CdS/15 nm TiO2 buffer layer. Because of the high resistivity of TiO2, thicker layers showed a strongly reduced FF and blocking behavior in the I–V characteristics, especially at lower temperatures. Recently a CdS-free CIGS device was presented with ALD-ZnTiO in combination with a sputtered ZnO layer as HTR window layers leading to a PCE of 12.5%, which was inferior to the CdS-containing reference device of 15.4%.[8]

In this contribution, ZnTiO is applied as single HTR layer with the goal of thinning the CdS layer <30 nm, hence improving the JSC of the PV cell by reducing the parasitic absorption in both CdS and ZnO without adversely affecting VOC. Thermal-ALD is used to deposit ZnTiO to mitigate sputtering damage on the CIGS surface and for a precise thickness control. The Ti content is controlled by means of pulse ratio. Differences in band-alignment due to a tunable band gap of ZnTiO are discussed in terms of temperature dependent I–V measurements.

Experimental Section

Sample Fabrication

The general device architecture is SLG/SiOx/Mo/CIGS/CdS/HTR/Al:ZnO/MgF2 where as HTR layer either sputtered ZnO or ALD-ZnTiO with a varying [Ti]/([Ti] + [Zn]) ratio is applied. CIGS was deposited on SiO and Mo coated soda lime glass (SLG) substrates by elemental coevaporation from effusion cells at a base pressure of ∼10–5 Pa in a multistage process as reported before.[18] Additionally a NaF/RbF PDT was performed by evaporation of alkali fluorides in the presence of Se vapor for 20 min each at a lower substrate temperature (Tsub decreases by 70 °C (NaF) and 120 °C (RbF) relative to the third stage). The absorber layer composition was measured by X-ray fluorescence giving a [Cu]/([In] + [Ga]) ratio of ∼0.94–0.97 and a [Ga]/([Ga] + [In]) ratio of ∼0.42. The absorber layer thickness of 3 μm was determined by scanning electron microscopy (SEM).

Prior to further processing the bare absorber was etched for 2 min in a 10%w KCN solution. The CdS layer was deposited by CBD with cadmium acetate (2.3 mM), thiourea (22 mM), and ammonium hydroxide (2 M [NH3]) at 70 °C for various times to adjust the layer thickness, that is, 10 min for ∼10 nm and 15 min for ∼30 nm. The Cd2+ partial electrolyte (PE) treatment was performed for 10 min and the conditions were similar to the CdS deposition only that no thiourea was added to the bath. A post-deposition annealing (2 min) at 180 °C and ambient atmosphere was performed for all samples directly after the chemical bath. For the samples which are not subjected to an ALD process (e.g., reference), an additional annealing at 100 °C in the ALD reactor for 15 h at 13 Pa Ar-atmosphere was performed in order to have an identical thermal history for all samples. SEM was used to determine the thickness for layers with a thickness above 20 nm. For thinner CdS layers, the thickness was estimated by reproducing the CdS absorption in the blue region of the EQE measurements using as input the extinction coefficient of CdS.

ZnO (∼80 nm) was deposited by a rf-magnetron sputtering process in an Ar/O2 (0.02%) atmosphere at a pressure of 0.46 Pa with a power density of 1.9 W cm–2. The ALD process was performed at a substrate temperature of 100 °C with Ar as carrier gas at a base pressure of 13 Pa in a Fiji G2 system (Ultratech). The precursors were diethylzinc (DEZ), tetrakis(dimethylamino)titanium(IV) (TDMAT), and H2O. TDMAT was kept at 75 °C while DEZ and H2O were unheated. ZnTiO was grown by a supercycle approach with a sequence of TiO2 and ZnO subcycles. A process with a subcycle ratio (1/3) for example consisted of one TiO2 cycle (H2O/Ar/TDMAT/Ar) and three ZnO cycles (H2O/Ar/DEZ/Ar) which were repeated until the desired thickness is reached. The growth rate was determined by ellipsometry on Si(100) reference substrates and compared to SEM micrographs which showed a similar thickness with a larger uncertainty. For either TiO2, ZnO, and ZnTiO a linear growth was observed with different growth rates: 0.053 nm/cycle for TiO2 and 0.166 nm/cycle for ZnO. Supercycling both processes for the deposition of ZnTiO was found to show a lower growth rate than a linear combination of the subcycle growth rates due to a different induction time of the subcycles, which is dependent on reactive sites and size and reactivity of the precursors. The (1/1) process for example gave 0.074 nm/cycle. No post deposition annealing was performed and the layers were found to be mostly amorphous (see GI-XRD in Figure S2) with increasing Ti content which is in accordance with a recent report.[8]

The cells were finished with a sputtered conductive Al:ZnO (2% wt Al2O3, 1.8 W cm–2) of ∼100 nm, 105 nm of MgF2 as antireflective coating, and 4 μm Ni/Al grid by e-beam evaporation. A cell area of 0.23 ± 0.02 cm2 was defined by mechanical scribing.

Characterization Methods

Current–voltage (I–V) characteristics were measured with a Keithley 2400 source meter and four-terminal sensing under standard test conditions (AM1.5G, 298 K) using a type ABA solar simulator. Temperature-dependent measurements were performed in a cryostat with liquid nitrogen cooling and a halogen lamp. External quantum efficiency (EQE) measurements were performed with a chopped white light source (halogen lamp), a triple-grating monochromator, and a Stanford Instruments lock-in amplifier under ∼100 W m–2 white light bias at 298 K. A monocrystalline Si solar cell certified by Fraunhofer ISE was used to calibrate the incoming light intensity. Transmission and reflectance measurements were performed on a Shimadzu UV-3600 spectrophotometer. X-ray diffraction (XRD) was performed on a Bruker D8 -diffractometer equipped with a CuKα source operated at 40 keV in grazing incidence (GI) geometry. SEM was performed on a Hitachi S-4800 electron microscope.

Annular dark-field scanning transmission electron microscopy (ADF-STEM) images were obtained using a Titan Themis TEM/STEM operated at 300 kV with a 3.9 nA beam current. Energy dispersive X-ray (EDX) mapping was performed with a sampling from 1.6 to 4.5 nm using a SuperX EDX detector in the same experimental setup. The cross-sectional sample for the STEM analysis was prepared by means of a FEI Helios NanoLab 600i focused ion beam operated at accelerating voltages of 30 and 5 kV.

XPS measurements were performed using a Quantum2000 from Physical Electronics with a monochromatic Al Kα source (1486.6 eV) operated at a base pressure below 8 × 10–7 Pa. The work function of the instrument is calibrated regularly to a binding energy of 83.95 eV (fwhm = 0.8 eV) for the Au 4f7/2 peak. The linearity of the energy scale is checked according to ISO 15472. The spectra were recorded with an energy step size of ΔE = 0.2 eV and a pass energy of Ep = 46.95 eV for core levels and ΔE = 0.05 eV with Ep = 23.50 eV for the valence band emission. An electron flood gun operated at 2.5 eV and an ion neutralizer using Ar+ of approximately 1 eV were used to minimize sample charging. A short Ar+ sputtering (500 eV, 60 s) was performed prior to the measurements to remove adventitious C from the surface. Depth profiles were obtained with Ar+ sputtering at 500 eV for 90s per step with a material removal rate estimated to be ∼7 nm per sputtering step. The Zn 2p3/2 and Ti 2p3/2 peaks were fitted with Gaussian–Lorentzian peaks and a Shirley background correction. Values given for the XPS determined [Ti]/([Ti] + [Zn]) compositions are mean average ±3σ over four peak fittings with varying the energy range for the background determination. The valence-band maximum position was obtained from the intercept of the linear extrapolation of the low binding energy edge of the valence band emission and the baseline of the noise level. The average value of six manual fits per measured curve was taken with the error presented being ≥3σ of these fits and not the absolute error.

Results and Discussion

In the following, the term process (1/p) will be used to address the ZnTiO layer which was grown by supercycling one TiO2 and p ZnO cycles resulting in a variable Ti content in the deposited layer (see Figure b). The ALD deposited ZnTiO was shown to have a tunable band gap in the investigated compositional range. In Figure a, a clear shift of the absorption onset toward higher energy is shown for process (1/7) up to process (1/2) (more data and the fitting procedure can be found in Figure S1). The indicators show the band gaps for each layer determined by the Tauc method[19] for a direct transition and in the case of process (1/3) and (1/2) also an indirect transition. With increasing Ti content, a shoulder in the α versus E function appears at about 4.5 eV indicating a contribution of a second transition. This makes the fitting procedure less trivial because the nature of the transition (direct or indirect) is unclear. A theoretical study on TiO2 indicates that the conduction band minimum (CBM) with Ti3d-like states is almost degenerate in the Γ-point and for anatase an indirect band gap is determined.[20] This might also be the case in ZnTiO but was not further investigated. By replacing ZnO with ZnTiO as HTR layer, already a slightly higher JSC is expected because a parasitic absorption loss of about 0.22 mA cm–2 is reported for CIGS devices with ZnO as HTR layer.[21] Furthermore, due to a refractive index between 2.0 and 2.2 (see Figure S3) ZnTiO is suitable in terms of optical management in a CIGS/CdS/ZnTiO/Al:ZnO structure.

Figure 1

(a) Absorption coefficient of ∼50 nm ZnTiO layers deposited on fused silica substrates. The indicators (square and triangle) correspond to the optical band gap derived by the Tauc method[19] for direct (square) or indirect (triangle) band gap (see Figure S1) and plotted in (b) against the Ti content determined by XPS on ∼50 nm ZnTiO layers deposited on Si.

Selected area electron diffraction and STEM/EDX studies on ZnTiO (same deposition conditions as for process (1/3)) deposited on a C-coated TEM grid and on a Si substrate were performed to assess its crystallinity and composition. The plan-view observations of the layer grown on the C-support film revealed an amorphous ZnTiO layer with homogeneous composition and a Ti atomic fraction of 21 ± 1% (see Figure ), which is in accordance to the XPS measurement (Figure b). Additionally, no changes in composition along the growth direction were detected from the cross-sectional observations from the ZnTiO layer grown on Si. GI-XRD measurements of ZnTiO deposited on fused silica substrates indicate also for process (1/2) and process (1/4) an amorphous structure (see Figure S2).

Figure 2

(a) SEM cross-sectional micrograph of a cleaved CIGS/CdS (∼15 nm)/ZnTiO (process (1/3), ∼60 nm). (b) Plan-view ADF-STEM micrograph and corresponding EDX chemical map of Ti (red) and Zn (green) of a ZnTiO layer (process (1/3), ∼50 nm) grown on an amorphous carbon coated TEM support grid, and (c) selected area electron diffraction pattern of the same ZnTiO layer on carbon support film shown in (b). (d) Cross-sectional ADF-STEM micrograph of a ZnTiO layer (process (1/3), ∼50 nm) grown on a Si substrate. An ∼2 nm SiO layer is present between the Si substrate and the ALD film. The crystallite size of ZnTiO is typically <1 nm (beam induced crystallization is observed during image acquisition). (e) EDX elemental maps of Ti, Zn, O, and Si obtained from the same sample as in (d) showing homogeneous composition along the growth direction.

In a first set of experiments, the application of ZnTiO as window layer in buffer-less CIGS devices was investigated. In order to have a defined surface for the NaF/RbF treated absorber comparable to the reference device with the CdS/sp-ZnO buffer a Cd2+ PE treatment was performed. Such a treatment was found to improve the device performance for CdS free CIGS cells.[22] Fifty nanometers of ALD-ZnTiO were deposited by supercycling process (1/5) 75 times, (1/4) 96 times, (1/3) 125 times, (1/2) 188 times. Comparing the I–V characteristics ALD-ZnTiO shows a significantly higher VOC and FF when compared to sp-ZnO. A trend toward higher VOC is observed with increasing Ti content (see Figure ) for the ALD-deposited HTR layer with the highest performance for process (1/3). For process (1/2), a photocurrent blocking behavior is observed with a strongly decreased FF. The highest PCE of 18.5% was achieved for process (1/3), which is significantly inferior to the 20.1% of the reference device with CdS buffer and sputtered ZnO HTR window layer. Comparing the EQE measurement of the CdS-free ZnTiO buffered cell and the reference device a flat loss over the visible spectrum is observed indicating stronger recombination losses which compensate the gain in the blue wavelength region from the substitution of CdS.

Figure 3

(a) J–V curves of SLG/SiO/Mo/CIGS/HTR/Al:ZnO/grid(Ni,Al)/MgF2 devices where the CIGS was treated with a Cd2+ PE treatment and either sputtered ZnO or ALD-ZnTiO was applied as HTR layer and the reference device with the structure SLG/SiO/Mo/CIGS/CdS/ZnO/Al:ZnO/grid(Ni,Al)/MgF2; (b) corresponding EQE measurement.

Similar to the approach reported previously,[11] in the following experiments CdS is kept as buffer layer, however, with a reduced thickness. PV-parameters for devices with an ∼15 nm CdS, i.e., half the standard thickness, are shown in Figure . The very thin CdS layer has already a strong beneficial influence on the VOC (compare Figures and 4). This is most evident in case of sp-ZnO as HTR layer. For the device Cd2+ PE/sp-ZnO, only about ∼540 mV was measured. In the device comprising a thin (∼15 nm) CdS/sp-ZnO buffer layer already ∼715 mV have been achieved with a larger value variance over a small area of the sample (six cells). For ALD-ZnTiO as HTR layer, again the highest VOC was found for process (1/3): for ∼15 nm CdS a VOC on par with the reference was obtained and no further improvement was seen with a thicker (30 nm) CdS layer (∼725 mV, see Figure S4). For process (1/2), again a strong photocurrent blocking was observed similar to the aforementioned buffer-less cells (for the I–V curve see Figure S6). The highest PCE for the experiments shown in Figure was achieved with process (1/4) due to the higher JSC. EQE measurements suggest a slightly reduced CdS thickness (∼10 nm) compared to the other samples in that experiment which might be related to sample handling, that is, it was removed first from the CBD bath. This deviation of the CdS thickness (15 vs 10 nm) did not show to influence the VOC of the devices comprising the ZnTiO HTR layer with relatively low Ti content (process (1/5) and (1/4)).

Figure 4

Boxplot chart (six best performing cells of each sample) of the I–V parameters of the device structure SLG/SiOx/Mo/CIGS/CdS/HTR/Al:ZnO/grid(Ni,Al)/MgF2 where a thin (∼15 nm) CdS buffer layer (t-CdS) is combined with either a sputtered ZnO (sp-ZnO) or ALD-ZnTiO with varying Ti content (process (1/2, 1/3, 1/4, 1/5) and compared to the respective reference device.

Therefore, in a next step the CdS thickness for process (1/3) was further reduced. The resulting I–V characteristics and EQE are given in Figure . The gain in JSC was estimated from the I–V characteristics to be ∼1 mA cm–2 and from integrating the EQE measurement with respect to AM1.5G to be ∼0.7 mA cm–2. A slight deviation is expected because the uncertainty for our EQE measurement in the region >3.1 eV is higher (see Figure ) and a difference in grid shading (in the EQE measurement not the full device is illuminated as in the I–V measurement) cannot be excluded. For the I–V measurement the difference in grid shading is expected to be within the statistical variation of the six best cells of each sample. An overall gain of ∼0.2% absolute of the median PCE over the reference device was achieved.

Figure 5

(a) Boxplot chart (six best performing cells of each sample) of the I–V parameters of devices with the structure SLG/SiOx/Mo/CIGS/CdS/HTR/Al:ZnO/grid(Ni,Al)/MgF2 where a reference device (∼30 nm CdS, HTR = sputtered ZnO) is compared to an alternative structure comprising a thin (∼10 nm) CdS (t-CdS) combined with ALD-ZnTiO (process (1/3)) as HTR layer; (b,c) corresponding EQE, reflectance, and J–V measurement. The dots in the EQE measurement for the curve t-CdS/ZTO (1/3) indicate the standard deviation of three consecutive measurements showing the higher uncertainty of the values in the short wavelength region.

The origin for the reduced FF (∼1% lower than the reference) of the device comprising ZnTiO as HTR layer can only partially be explained by an increased series resistance (RS) (see Figures , S5, and S7). Hence temperature-dependent I–V measurements were performed from 123 to 323 K. Figure shows the obtained curves for process (1/4), process (1/3), process (1/2), and the reference device. All structures show a nonideality, i.e., a change of slope at high voltages (above VOC) which has been reported when KF PDT was applied but is usually not seen for cells exposed to a NaF PDT only.[23] The RbF PDT performed on all absorbers is supposed to be the origin of this behavior with the surface modification introducing two parallel conduction paths which act as barriers with different activation energies impeding charge carrier transport.[24] For process (1/3) a strong photocurrent blocking, i.e., voltage dependent collection, is observed for temperatures <233 K. For process (1/4) this is not observed until the lowest investigated temperature (122 K, see inset in Figure a) and not at all for the reference device. For process (1/2), a strong photocurrent blocking is observed already at 298 K strongly reducing JSC and FF. Upon heating the device to 348 K the FF improves as shown in Figure c. Furthermore, the cells show positive light soaking characteristics (see Figure S6). This behavior may be related to a conduction band offset (CBO) introduced by the ZnTiO layer with a positive offset for process (1/2). Numerical simulations (SCAPS) of the band alignment at the buffer/HTR interface influencing the I–V characteristics propose that a certain limit for a positive CBO is tolerated until FF and JSC are drastically reduced. This limit is modeled to be ∼+0.1 to +0.3 eV by Inoue et al.[25] In their model, this value shifts depending on the position, concentration, and type of interface defects introduced at the buffer/HTR interface and is further dependent on the CBO at the CIGS/buffer interface. Because the optical band gap of ZnTiO varies with the Ti content the analysis of the valence band can give insights on whether the valence or conduction bands are influenced by the compositional change. From XPS measurements of ZnTiO (50 nm) deposited on a Si wafer the (EZnZn – EZn) values, i.e., the difference in binding energy between the Zn 2p3/2 core level and the valence band, were determined (see Table ). This allows the comparison of values while neglecting band bending and charging effects influencing the energy scale.[26] Similar values were obtained which indicates that the change in optical band gap is due to a shift of the conduction band. This supports the hypothesis derived from the temperature-dependent I–V measurements that a band discontinuity is present in the conduction band between the ZnTiO and the interface to the absorber which is positive for process (1/2).

Figure 6

Temperature dependent J–V measurements from 123 to 323 K (a,b,d) and 278 to 348 K (c) at temperature steps of 10 K. The common device structure is SLG/SiOx/Mo/CIGS/CdS/HTR/Al:ZnO/grid(Ni,Al)/MgF2 where (a–c) comprise a thin (∼10 nm) CdS with ALD-ZnTiO process (1/4) (a), process (1/3) (b), and process (1/2) (c) as HTR layer and (d) is the reference structure with a standard (∼30 nm) CdS and sputtered ZnO as HTR layer. The inset in (a,d) is a magnification around Vmpp to emphasize low-temperature behavior.

Table 1

Core Level to Valence-Band Maximum Binding Energy Difference (eV) of ALD-ZnTiO (50 nm) on Si Determined by XPS

ZnxTiyO process	(1/7)	(1/5)	(1/4)	(1/3)	(1/2)
EZn 2p3/2 – EvZnxTiyO (eV)	1018.8 ± 0.15	1018.8 ± 0.15	1018.7 ± 0.15	1018.6 ± 0.15	1018.6 ± 0.15

Conclusion

In conclusion, an ALD- ZnTiO layer was used to substitute sputtered ZnO in CIGS solar cells with the aim of reducing the CdS thickness. The low temperature deposited ZnTiO was found to be amorphous with the optical bandgap widening with increasing Ti content. XPS measurements suggest that this shift is due to a change in the conduction band rather than the valence band. This influences the conduction band alignment between ZnTiO and the CdS buffer layer introducing a strong photocurrent blocking at RT for the highest investigated Ti content, which is also observed for a lower Ti content at reduced temperatures. The compositional optimum of ZnTiO for CIGS solar cells in this study was found to have a [Ti]/([Ti] + [Zn]) atomic fraction of ∼0.21. A CdS-free device with 18.5% efficiency was achieved. When combining ZnTiO with a thin (∼10 nm) CdS layer, a PCE of 20.8% was achieved for the champion device which is slightly superior to the reference device with sputtered ZnO as HTR layer. A significant gain in JSC was observed which is mainly due to the reduced parasitic absorption of the ∼10 nm CdS compared to the ∼30 nm CdS in the reference structure. For the thin CdS/ZnTiO buffer/HTR system a decreased FF was found compared to the reference structure comprising sputtered ZnO as HTR layer. The lower FF might be related to impeded electron transport via the aforementioned conduction band discontinuity and an increased series resistance. To further improve the device efficiency via an improved FF, more parameters such as deposition temperature and doping of ZnTiO should be investigated with respect to their influence on conductivity and band alignment.