Literature DB >> 29956911

Doping-Free Complementary Logic Gates Enabled by Two-Dimensional Polarity-Controllable Transistors.

Giovanni V Resta1, Yashwanth Balaji2,3, Dennis Lin2, Iuliana P Radu2, Francky Catthoor2,3, Pierre-Emmanuel Gaillardon4, Giovanni De Micheli1.   

Abstract

Atomically thin two-dimensional (2D) materials belonging to transition metal dichalcogenides, due to their physical and electrical properties, are an exceptional vector for the exploration of next-generation semiconductor devices. Among them, due to the possibility of ambipolar conduction, tungsten diselenide (WSe2) provides a platform for the efficient implementation of polarity-controllable transistors. These transistors use an additional gate, named polarity gate, that, due to the electrostatic doping of the Schottky junctions, provides a device-level dynamic control of their polarity, that is, n- or p-type. Here, we experimentally demonstrate a complete doping-free standard cell library realized on WSe2 without the use of either chemical or physical doping. We show a functionally complete family of complementary logic gates (INV, NAND, NOR, 2-input XOR, 3-input XOR, and MAJ) and, due to the reconfigurable capabilities of the single devices, achieve the realization of highly expressive logic gates, such as exclusive-OR (XOR) and majority (MAJ), with fewer transistors than possible in conventional complementary metal-oxide-semiconductor logic. Our work shows a path to enable doping-free low-power electronics on 2D semiconductors, going beyond the concept of unipolar physically doped devices, while suggesting a road to achieve higher computational densities in two-dimensional electronics.

Entities:  

Keywords:  WSe2; electrostatic doping; logic gates; polarity control; reconfigurable; standard cell library; two-dimensional semiconductor

Year:  2018        PMID: 29956911     DOI: 10.1021/acsnano.8b02739

Source DB:  PubMed          Journal:  ACS Nano        ISSN: 1936-0851            Impact factor:   15.881


  5 in total

1.  An application-specific image processing array based on WSe2 transistors with electrically switchable logic functions.

Authors:  Senfeng Zeng; Chunsen Liu; Xiaohe Huang; Zhaowu Tang; Liwei Liu; Peng Zhou
Journal:  Nat Commun       Date:  2022-01-10       Impact factor: 14.919

2.  Highly sensitive active pixel image sensor array driven by large-area bilayer MoS2 transistor circuitry.

Authors:  Seongin Hong; Nicolò Zagni; Sooho Choo; Na Liu; Seungho Baek; Arindam Bala; Hocheon Yoo; Byung Ha Kang; Hyun Jae Kim; Hyung Joong Yun; Muhammad Ashraful Alam; Sunkook Kim
Journal:  Nat Commun       Date:  2021-06-11       Impact factor: 14.919

3.  Logic-in-memory based on an atomically thin semiconductor.

Authors:  Guilherme Migliato Marega; Yanfei Zhao; Ahmet Avsar; Zhenyu Wang; Mukesh Tripathi; Aleksandra Radenovic; Andras Kis
Journal:  Nature       Date:  2020-11-04       Impact factor: 49.962

4.  Bottom-Gate Approach for All Basic Logic Gates Implementation by a Single-Type IGZO-Based MOS Transistor with Reduced Footprint.

Authors:  Shaocheng Qi; Joao Cunha; Tian-Long Guo; Peiqin Chen; Remo Proietti Zaccaria; Mingzhi Dai
Journal:  Adv Sci (Weinh)       Date:  2020-01-24       Impact factor: 16.806

5.  Graphene/Ferroelectric (Ge-Doped HfO2) Adaptable Transistors Acting as Reconfigurable Logic Gates.

Authors:  Mircea Dragoman; Adrian Dinescu; Daniela Dragoman; Cătălin Palade; Valentin Şerban Teodorescu; Magdalena Lidia Ciurea
Journal:  Nanomaterials (Basel)       Date:  2022-01-17       Impact factor: 5.076

  5 in total

北京卡尤迪生物科技股份有限公司 © 2022-2023.