| Literature DB >> 29659508 |
Sukho Oh1, DongYeop Hwang2, Ki-Hyung Kim3, Kangseok Kim4.
Abstract
Time Slotted Channel Hopping (TSCH) is widely used in the industrial wireless sensor networks due to its high reliability and energy efficiency. Various timeslot and channel scheduling schemes have been proposed for achieving high reliability and energy efficiency for TSCH networks. Recently proposed autonomous scheduling schemes provide flexible timeslot scheduling based on the routing topology, but do not take into account the network traffic and packet forwarding delays. In this paper, we propose an autonomous scheduling scheme for convergecast in TSCH networks with RPL as a routing protocol, named Escalator. Escalator generates a consecutive timeslot schedule along the packet forwarding path to minimize the packet transmission delay. The schedule is generated autonomously by utilizing only the local routing topology information without any additional signaling with other nodes. The generated schedule is guaranteed to be conflict-free, in that all nodes in the network could transmit packets to the sink in every slotframe cycle. We implement Escalator and evaluate its performance with existing autonomous scheduling schemes through a testbed and simulation. Experimental results show that the proposed Escalator has lower end-to-end delay and higher packet delivery ratio compared to the existing schemes regardless of the network topology.Entities:
Keywords: RPL; TSCH; autonomous scheduling; convergecast; wireless sensor network
Year: 2018 PMID: 29659508 PMCID: PMC5948937 DOI: 10.3390/s18041209
Source DB: PubMed Journal: Sensors (Basel) ISSN: 1424-8220 Impact factor: 3.576
Figure 1An example of the Escalator schedule: (a) network topology of the example; (b) Escalator’s generated schedule for the example.
Main notations.
| Symbol | Definition |
|---|---|
|
| The network consisting of nodes |
|
| The number of nodes in the network |
|
| The set of nodes in the network |
|
| The set of links in the network |
|
| Duration of timeslot |
|
| The number of available orthogonal channel |
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| The channel offset that is used for multiple channel usage at a single timeslot |
|
| The channel offset used for |
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| The total number of timeslots that have elapsed since the start of the network |
|
| The convergecast slotframe |
|
| The baseline slotframe |
|
| The size of slotframe |
|
| A node with ID |
|
| The preferred parent of node |
|
| The set of the direct child nodes of node |
|
| The set of nodes in the sub-graph of node |
|
| A link for which the sender is |
|
| Hop count of node |
|
| Operation at timeslot |
|
| The operation in which |
|
| The operation in which |
|
| The operation in which |
| to the parent node | |
|
| The operation in which |
| from one of the child nodes | |
|
| The timeslot section from |
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| Least common multiple of |
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| Maximum hop counts of the packet-forwarding path in network |
|
| Average end-to-end delay of node |
|
| Average bandwidth of node in network |
|
| Average required buffer capability of nodes in network |
Figure 2An example of timeslot allocation for the convergecast slotframe.
Figure 3An example of the sliding slotframe.
Figure 4An example of the rank of links.
Figure 5An example of the Escalator schedule. DODAG, Destination-Oriented Directed Acyclic Graph.
Figure 6Timeslots of the convergecast slotframe where collisions should be avoided.
Figure 7Timeslot section where collisions should be avoided. (a) A case where the baseline slotframe size (17) is greater than the convergecast slotframe size (12); (b) a case where the baseline slotframe size (11) is smaller than the convergecast slotframe size (12).
Figure 8Conflicts in TDMA wireless networks.
Figure 9Testbed and simulation topologies.
Figure 10Testbed results: (a) end-to-end delay by packet transmission hop when the packet transmission interval is 20 s; (b) end-to-end delay by packet transmission hop when the packet transmission interval is 5 s; (c) PDR per the packet transmission interval.
Figure 11End-to-end delay per packet delivery hops in the simulation: (a) a packet transmission interval of 20 s on the grid; (b) a packet transmission interval of 5 s on the grid; (c) a packet transmission interval of 20 s on the grid; (d) a packet transmission interval of 5 s on the grid.
Figure 12PDR per packet transmission interval in the simulation.
Measured average and max duty cycle in the simulations.
| Duty Cycle (%) | ||||||||
|---|---|---|---|---|---|---|---|---|
| Average | Max | Average | Max | Average | Max | Average | Max | |
| minimal | 2.40 | 2.47 | 2.44 | 2.77 | 2.41 | 2.61 | 2.48 | 2.96 |
| Orchestra 37 | 1.06 | 1.65 | 1.20 | 2.56 | 1.15 | 2.46 | 1.31 | 2.83 |
| Orchestra 53 | 0.89 | 1.34 | 1.02 | 1.96 | 0.96 | 1.68 | 1.08 | 2.10 |
| Escalator 73 | 0.92 | 2.67 | 1.12 | 3.65 | 1.20 | 3.05 | 1.54 | 5.31 |
| Escalator 107 | 0.78 | 1.64 | 0.98 | 2.39 | 0.99 | 4.01 | 1.32 | 6.85 |
Figure 13Duty cycle per number of routing entries in a node: (a) a packet transmission interval of 20 s on the grid; (b) a packet transmission interval of 5 s on the grid; (c) a packet transmission interval of 20 s on the grid; (d) a packet transmission interval of 5 s on the grid.