A Semi-Analytical Extraction Method for Interface and Bulk Density of States in Metal Oxide Thin-Film Transistors.

A semi-analytical extraction method of interface and bulk density of states (DOS) is proposed by using the low-frequency capacitance-voltage characteristics and current-voltage characteristics of indium zinc oxide thin-film transistors (IZO TFTs). In this work, an exponential potential distribution along the depth direction of the active layer is assumed and confirmed by numerical solution of Poisson's equation followed by device simulation. The interface DOS is obtained as a superposition of constant deep states and exponential tail states. Moreover, it is shown that the bulk DOS may be represented by the superposition of exponential deep states and exponential tail states. The extracted values of bulk DOS and interface DOS are further verified by comparing the measured transfer and output characteristics of IZO TFTs with the simulation results by a 2D device simulator ATLAS (Silvaco). As a result, the proposed extraction method may be useful for diagnosing and characterising metal oxide TFTs since it is fast to extract interface and bulk density of states (DOS) simultaneously.

1. Introduction

Thin film transistors (TFTs) are one kind of field-effect transistors (FETs). Their structure and operation principles are similar to those of metal oxide semiconductor field effect transistors (MOSFETs), which are commonly used in modern integrated circuits (ICs) [1]. Amorphous oxide semiconductor thin-film transistors (AOS TFTs) are considered one of the most promising technologies for flat panel display (FPD) due to transparency, good uniformity, higher mobility than hydrogenated amorphous silicon TFTs (a-Si:H TFTs), good process compatibility with a-Si TFTs, and a lower temperature fabrication process than low temperature poly-silicon (LTPS) TFTs [2,3,4,5]. The electrical characteristics of AOS TFTs are significantly affected by the bulk density of states (DOS) in the active layer and the interface density of states between the gate insulator and the active layer. The bulk DOS may be attributed to structural disorder (bond angles and length variations), dangling bonds, non-stoichiometry, and carrier scattering in the amorphous films [6]. The interface DOS may be caused by defects located at the interface, which can exchange charge with the active layers by capturing or emitting electrons [7]. It is important to extract DOS of TFTs for device design, process characterization, or modeling. Several methods have been developed to extract only the bulk DOS, such as numerical calculations [8], optical illumination [9], temperature-dependent characteristics [10], or multi-frequency current–voltage (C–V) characteristics [11]. However, it is usually difficult to extract the interface DOS and the bulk DOS simultaneously.

Lui et al. [12] and Kimura [13] extracted the interface and bulk density of states in TFTs from the characteristics of capacitance–voltage and current–voltage based on the numerical iterative solution of Poisson’s equation. However, the numerical iterative solution generally has the disadvantages of operation complexity, long computational time, and possible convergence problems. Hastas et al. extracted interface trap states from analysis of the transfer characteristics in the sub-threshold region and the bulk trap states by numerically fitting the surface potential equation [14]. Tsuji et al. extracted the interface trap density based on an expression of interface trap charge density (Q) as functions of the front and back-side surface potentials, in which the electric field at the back side is assumed to be zero [15]. Therefore, it is essential to develop analytical methods for extracting both the interface DOS and the bulk DOS of TFTs.

In this work, we propose a semi-analytical method to extract the interface DOS and the bulk DOS in indium zinc oxide (IZO) TFTs simultaneously by only using the low-frequency capacitance–voltage characteristics and current–voltage characteristics.

2. Extraction Method

Figure 1a shows a schematic cross-sectional view of indium zinc oxide (IZO) TFTs with inverted staggered bottom gate structure. The IZO material as the channel layer has the advantages of transparency, high mobility, and excellent drain current saturation [16]. Figure 1b shows the energy band diagram of the device, in which the surface potential (Ψ) and the back interface potential (Ψ) are respectively labeled. Poisson’s equation is given by where n and n are the free electron concentration and localised trapped electron concentration, respectively.

Figure 1

(a) Cross-sectional view of indium zinc oxide thin-film transistors (IZO TFTs) with inverted staggered bottom gate structure; (b) energy band diagram along the thin-film depth direction of IZO TFTs.

Using the relationship , we can get

Substituting Equation (1) into Equation (2) and differentiating both sides with respect to Ψ, we have where ρ(Ψ) is the surface charge concentration, and ρ(Ψ) is the back interface charge concentration. Equations (3) and (4) can be further rearranged as

Based on Gauss’s theorem, the surface charge per unit area in the channel (Q) considering the effect of the back interface potential can be expressed as

In this paper, the potential distribution along the depth direction (x) of the active layer is assumed as where x0 is the characteristic length of the potential distribution. Note that the assumption for Equation (8) will be confirmed by the numerical solution of Poisson’s equation in Appendix A and the device simulation in Section 3. Substituting Equation (8) into Equations (5)–(7), we have While in [12], the surface charge at the back interface was not taken into account.

The differential of surface potential with respect to gate-source bias can be expressed as [17] where C(V) is gate capacitance at some V, C is the gate oxide capacitance per unit area, and Q is the charge per unit area at the gate electrode

The nonlinear relation between Ψ and V can be obtained by integrating Equation (12) over V: where V is the flat band voltage.

The free charge density per unit area (Q) can be expressed by an integration of n(x) over x. where ts is the thickness of the active layer, n0 is the flat band electron concentration, and V is the thermal voltage (kT/q). On the other hand, Q can also be obtained from the transfer characteristics of TFT at low V.

Note that n0 can be extracted from Equation (15) equal to Equation (16) at the condition of flat band, i.e., Ψ 0 and V = V. Then, x0 at some V can be calculated from Equation (15) equal to Equation (16) by numerical integration.

Furthermore, based on the charge conservation relationship Q 0, where Q is the effective interface charge per unit area at the gate insulator, one obtains

Thus, the interface density of states (N) can be calculated by differentiating Q0 with respect to Ψ where E0 is the bulk Fermi level of the active layer, which is calculated from the relationship of n0 to E0 : where NC is the effective density of states in the conduction band with a typical value of 5 × 1018 cm−3 [18].

Furthermore, based on the surface potential Ψ given by Equation (14) and the surface charge concentration ρ(Ψ) given by Equation (9), the bulk density of states can be given by [17]

The extraction procedure of DOS is described as follows. Firstly, Ψ with respect to V is obtained from the C–V characteristics of TFTs by Equation (14). Secondly, x0 can be calculated from the current characteristics of TFTs by using Equations (15) and (16). Thirdly, ρ(Ψ), Q, and Q will be subsequently obtained by Equations (9), (11), and (17), respectively. Finally, the interface density of states (N(E)) and the bulk density of states (N(E)) can be extracted by Equations (18) and (20), respectively. As a result, the extraction method may be easily realised step by step as seen from the above extraction procedure.

3. Results and Discussion

The fabrication process of the IZO TFTs is described as follows. A gate electrode of molybdenum (Mo, 200 nm) is deposited by direct current (DC) sputtering. Subsequently, a 300 nm gate insulator (SiO2) was deposited by plasma-enhanced chemical vapor deposition (PECVD). A 30 nm IZO active layer is deposited by using a radio frequency (RF) magnetron system with the segregated target of IZO (In2O3:ZnO = 1:1). Then, an etch stopper layer (ESL) SiO2 is deposited by PECVD to protect the active layer. Finally, a 200nm Mo is formed by sputtering as S/D electrodes. The channel length and width of IZO TFTs are determined by layout and patterned by the conventional lithographic techniques.

The current–voltage (I–V) and C–V characteristics of TFTs are measured by using a probe station and a semiconductor parameter analyser (Agilent B1500, Agilent Technologies Inc., Santa Clara, CA, USA). The transfer characteristics are measured by scanning the gate-source voltage (V) from −10 V to 10 V with the step of 0.1 V at the condition of V = 0.1 V. The C–V characteristics are measured by superimposing the AC voltage signal (amplitude = 200 mV, frequency = 1 kHz) to DC gate bias in the condition of source and drain electrodes connected together. Note that those measurements are done at room temperature in the dark air ambient. It is thought that the DOS distribution of AOS TFTs remains unchanged at different temperatures [10]. Figure 2a shows the transfer characteristics of IZO TFTs (W/L = 20 μm/10 μm). The threshold voltage, the field-effect mobility, sub-threshold swing (SS), and on/off current ratio (Ion/Ioff) of the pristine TFTs are extracted to be 1.8 V, 12.36 cm2/(V·s), 0.23 V/dec, and 1 × 107, respectively. V is extracted as 0.6 V from the I–V characteristics following the method developed by Migliorato et al. [19]. n0 is extracted as 3.84 × 1016 cm−3 by (15) when Ψ 0, i.e., V = V. Figure 2b shows the C–V characteristics of the devices at the frequency of 1 kHz, which are measured with source and drain electrodes combined together. Note that the frequency of 1 kHz for the AC signal may be low enough to make the TFTs work in the quasi-static conditions. Figure 3 shows the surface potential (Ψ) with respect to V from (14) based on the C–V characteristics and the value of V. Figure 2c shows the micrograph of IZO TFTs with W/L = 20 μm/10 μm.

Figure 2

Experimental data of IZO TFTs (W/L = 20 μm/10 μm). (a) Transfer characteristics; (b) C characteristics; (c) The micrograph of the devices.

Figure 3

Ψ versus V obtained by (14) based on the capacitance–voltage (C–V) characteristics.

For further verification of (8), we perform the device simulation by the 2D device simulator ATLAS (Silvaco) for the IZO TFTs as described above. Figure 4 shows the distribution of the potential along the depth direction (x) at the conditions of V = 2.0 V, V = 0.1 V. It is found that the proposed Equation (8) can fit the simulated potential distribution well. Note that at other values of Vgs including that at the subthreshold region, the simulated potential distributions are also found to be well fitted by Equation (8) with different values of x0. As a result, Equation (8) may be reasonable and correct for reproducing the potential distribution of the thin active layer. Furthermore, based on the I–V characteristics and the surface potential distribution as seen in Figure 3, the value of x0 can be extracted from Equation (15) equal to Equation (16), as shown in Figure 5. It is found that the value of x0 tends to vary slowly when V is larger than the threshold voltage, because the variation of Q changes more slowly for TFTs working in the above-threshold region.

Figure 4

The potential distribution simulated by a 2D device simulator ATLAS.

Figure 5

The calculated results of x0 versus V.

Figure 6 shows the extracted interface density of states profile calculated from Equation (18). It is found that the interface DOS distribution is quite flat for the energy far from E, while it linearly increases with the increase of energy close to E at the exponent coordinate. Then, the interface DOS of AOS TFTs may be divided into two parts: constant deep states and exponential tail states, i.e., where N is the density of deep states, N is the density tail states at the conduction edge, and E is the characteristic energy of tail states. For details, N/N is extracted by extrapolating the deep/tail states to E = EC, and E is extracted from the slope of log(N) versus (E − EC) for the tail states. The extracted values are N = 1.3 × 1012 cm−2 eV−1, N = 2.9 × 1012 cm−2 eV−1, E = 0.08 eV. Obviously, the interface DOS distribution can be used to characterise interface quality and the reliability of AOS TFTs [20,21].

Figure 6

Extracted interface density of states (DOS) as a function of E − E from the proposed method (symbols) and results fitted by (21) (solid lines).

Figure 7 shows the bulk density of states profile extracted from Equation (20). It is observed that the bulk DOS distribution slowly increases with the increase of the energy far from E, while it quickly increases with the increase of energy close to E at the exponent coordinate. It is found that the bulk DOS may be a superposition of exponential deep states and exponential tail states, i.e., where N/N is the density of deep/tail states at the conduction edge and E/E is the characteristic energy of deep/tail states, of which the extraction method is similar to that of interface DOS as described above. The extracted values are N = 6.0 × 1016 cm−3 eV−1, E = 5.0 eV, N = 6.5 × 1017 cm−3 eV−1, and E = 0.10 eV. Such double exponential distribution for the bulk DOS can also be seen in other previously reported works [8,9,10,11]. For details, the deep states in AOSs may derive from oxygen deficiency, while the tail states originate from the variation of In–O–metal bonding angles [22].

Figure 7

Extracted bulk DOS as a function of E − E from the proposed method (symbols) and results fitted by (22) (solid lines).

The device simulation is performed by a 2D device simulator ATLAS (Silvaco, Silvaco International, Santa Clara, CA, USA) to verify the proposed method, where the extracted values of interface DOS and bulk DOS are inserted into the simulator. The other parameters of IZO TFTs in the simulation are the same as those of the fabricated IZO TFTs. As seen from Figure 8, the simulation results exhibit a good agreement with the measured transfer and output characteristics of IZO TFTs. In brief, the proposed extraction method for interface and bulk DOS is valuable for the application in metal oxide TFTs.

Figure 8

Experimental data (symbols) and simulated results (solid lines) of IZO TFTs with W/L = 20 μm/10 μm. (a) Transfer characteristics; (b) output characteristics.

4. Conclusions

In this paper, we propose a semi-analytical extraction method for the interface DOS and the bulk DOS of IZO TFTs by using the low-frequency C–V characteristics and I–V characteristics. It is shown that the interface DOS is extracted as a superposition of constant deep states and exponential tail states with N = 1.3 × 1012 cm−2 eV−1, N = 2.9 × 1012 cm−2 eV−1, and E = 0.08 eV. Additionally, the bulk DOS is extracted as the superposition of exponential deep states and exponential tail states with N = 6.0 × 1016 cm−3 eV−1, E = 5.0 eV, N = 6.5 × 1017 cm−3 eV−1, and E = 0.10 eV. Furthermore, the device simulation is performed by a 2D device simulator to verify the extracted values of interface DOS and bulk DOS. It is found that there is a good agreement between simulation results and the measured transfer and output characteristics of IZO TFTs. Hence, the proposed extraction method for interface and bulk DOS may be valuable for characterising metal oxide TFTs due to the advantages of being semi-analytical and fast. Since the proposed extraction method is directly deduced from Poisson’s equation, it may also be applied in other types of TFTs, such as a-Si:H TFTs, polysilicon TFTs, or organic TFTs.