Side Gate Tunable Josephson Junctions at the LaAlO3/SrTiO3 Interface.

Novel physical phenomena arising at the interface of complex oxide heterostructures offer exciting opportunities for the development of future electronic devices. Using the prototypical LaAlO3/SrTiO3 interface as a model system, we employ a single-step lithographic process to realize gate-tunable Josephson junctions through a combination of lateral confinement and local side gating. The action of the side gates is found to be comparable to that of a local back gate, constituting a robust and efficient way to control the properties of the interface at the nanoscale. We demonstrate that the side gates enable reliable tuning of both the normal-state resistance and the critical (Josephson) current of the constrictions. The conductance and Josephson current show mesoscopic fluctuations as a function of the applied side gate voltage, and the analysis of their amplitude enables the extraction of the phase coherence and thermal lengths. Finally, we realize a superconducting quantum interference device in which the critical currents of each of the constriction-type Josephson junctions can be controlled independently via the side gates.

Complex oxide heterostructures host a diverse set of novel physical phenomena which, in combination with an ever-advancing degree of experimental control, shows their promise for fundamental discovery and technological applications.[1,2] Over the past decade, the creation and control of interface superconductivity in oxide heterostructures has attracted a great deal of attention, with special emphasis on the two-dimensional electron system (2DES) hosted at the interface between the two wide band gap insulators LaAlO3 (LAO) and SrTiO3 (STO).[3,4] Superconductivity at the LAO/STO interface occurs in an exotic environment with strong spin-orbit coupling[5−7] in coexistence with localized magnetic moments[8,9] and ferroelastic domains.[10,11] Moreover, the superfluid density can be tuned using the electrostatic field-effect,[12] allowing for an on-off switch of superconductivity by means of an externally applied gate voltage.[13,14] Despite substantial experimental efforts[12,15,16] accompanied by a growing body of theoretical works,[17−19] the microscopic details of superconductivity in the system are still not completely understood. Efforts to clarify this question have propelled the realization of devices to perform phase-sensitive measurements, opening the possibility to garner information about the symmetry of the superconducting order parameter of the system.[12,15] Josephson coupling has recently been reported in STO-based 2DESs, first in top-gated structures where the weak link is electrostatically defined,[20−22] and later in constriction-type Josephson junctions (c-JJ).[23] Quantum interference was observed through the integration of two such weak links in a superconducting loop, forming a superconducting quantum interference device (SQUID).[23] While the top-gating approach benefits from the ability to independently tune each of the weak links, it is rather complex due to the requirement of multiple aligned lithography steps. Moreover, it is well-established that the properties of the 2DES at the LAO/STO interface are extremely sensitive to metal and chemical adsorption[24−26] at the surface. These problems can be overcome by employing the simpler c-JJ approach, which requires only a single lithographic step and no further processing after the LAO growth. However, it remains to be shown whether local tunability can be achieved in such weak links.

In this work, we explore a side gate geometry in order to realize gate-tunable c-JJs at the LAO/STO interface. We demonstrate local electrostatic tunability of these c-JJs while preserving a single lithographic step process by simultaneously defining both the constrictions and the side gate electrodes. Similar approaches are often employed in conventional semiconductor based 2DESs to obtain lateral confinement and electrostatically control the effective channel width.[27] Here, however, we find the electric-field dependence of the STO permittivity to play a crucial role, rendering the action of the side gates comparable to that of an effective “local back gate”. For a single junction, phase-coherent transport gives rise to mesoscopic fluctuations of the conductance and of the (Josephson) critical current as a function of side gate voltage. The amplitude of these fluctuations enables us to extract the phase coherence and thermal lengths. Furthermore, we demonstrate the reliability of the side gate electrodes to locally and independently tune the weak links by integrating two side gated c-JJs in a SQUID and controlling the (a)symmetry of its response.

Device fabrication relies on a prepatterning technique[28,29] involving a single lithographic step, which makes use of a template to define the insulating regions on the STO substrate prior to the epitaxial growth of the LAO thin film. Starting from a TiO2-terminated STO(001) substrate, we first pattern a resist mask using electron-beam lithography. After development, a thin (13 nm) AlO layer is deposited by sputtering, and the remaining resist is removed by lift-off in acetone. As a result, the areas of the STO surface protected by the resist during AlO deposition are cleared, whereas the exposed regions are coated by AlO. Next, a 12 u.c. LAO film is deposited by pulsed laser deposition. In the areas where the STO surface is exposed, the LAO film grows crystalline (c-LAO), and the 2DES forms at the interface. The regions covered by AlO, where the LAO film grows amorphous (α-LAO), remain insulating. The growth process is monitored in situ using reflection high energy electron diffraction (RHEED), displaying a layer-by-layer growth mode. The LAO films were grown at two different temperatures, namely, 770 °C and 840 °C. Lower growth temperature results in samples with higher sheet resistance, whereas samples grown at higher temperature exhibit a lower sheet resistance and superconductivity. A more detailed description of the fabrication process can be found in the Supporting Information. A 3D schematic of a side gated constriction is shown in Figure a. The AlO mask delimits the areas where the channel, the bonding pads, and the side gate electrodes are formed. An atomic force microscopy (AFM) image of a constriction and the two side gates is presented in Figure b. The height profile in Figure c reveals a channel width (w) of approximately 50 nm. We have fabricated different devices varying the distance between the side gates and the conducting channel and the growth temperature of the LAO thin film. The parameters of the constriction devices presented in this work are summarized in Table , and all devices show qualitatively similar behavior.

Figure 1

(a) 3D schematic of a side gated constriction. α-LAO: amorphous LAO; c-LAO: crystalline LAO. (b) AFM image of a typical device showing the constriction and two side gates (SG1 and SG2). The 2DES is formed only at the interface between c-LAO and STO. (c) Height profile along the black line in panel b, showing a constriction width of approximately 50 nm.

Table 1

Parameters of the Side Gate Devices Presented in This Work: Width (w) and Length (L) of the Conducting Channel, Distance between the Channel and the Side Gates (d), and the Growth Temperature of the LAO Thin Film (Tgrowth)

	Dev1	Dev2	Dev3
w (nm)	50	50	50
L (nm)	500	500	500
d (nm)	200	100	100
Tgrowth (°C)	770	770	840

The measurement configuration used is shown in Figure a. A constant DC current (Ibias) is injected through the conducting channel and the voltage drop (V) is locally measured at the constriction using two probes on the side. Voltages can be applied independently to the two side gates (VSG1 and VSG2), enabling local modulation of transport across the constriction by field-effect. In order to understand how the local side gates modulate transport through the constriction in this geometry, we performed finite element analysis (FEA) in COMSOL (see Supporting Information for modeling specific details). Calculations are performed for the geometry sketched in Figure b, using a channel width w ≈ 50 nm and a distance d ≈ 100 nm between the side gates and the channel. An important aspect that has to be addressed is the role of the strong electric-field dependence of the permittivity of the STO substrate, which is not commonly found in other systems. Its electric-field dependence is modeled as[30,31]with B = 23 500 and E0 = 82 000 V/m.[32] The side gate electrodes are modeled as areas of fixed voltage and the conducting channel as a ground plane. This approximation is valid provided the voltage drop across the constriction is negligible when compared to the magnitude of the voltages applied to the side gate electrodes.

Figure 2

(a) Sketch of the device geometry showing the electrical connections for transport measurements. (b) Spatial map of the out-of-plane electric polarization (P) for VSG1,2 = −50 mV, obtained by finite-element simulations. (c and d) Evolution of P and εSTO, respectively, across the constriction (along the white line in panel b) for different values of VSG1,2. (e) Value of P at the center of the constriction (x = 0 nm) as a function of VSG1,2. (f) ΔP as a function of VSG1,2. Color code as in panel e. Inset: electric polarization profiles across the constriction.

Figure b shows a spatial map of the calculated out-of-plane electric polarization (P) in a symmetric gating configuration with VSG1,2 = −50 mV. The out-of-plane polarization is directly related to the accumulated charge carrier density at the interface by Δn2D = P/e. Due to the coplanar capacitor arrangement, crowding of electric-field lines occurs at the edges of the constriction. Figure c shows the resulting variation of P across the channel (white line in Figure b) for different values of VSG1,2. For all of the curves, the magnitude of P is maximum at the edges of the channel and minimum at its center. In turn, the enhancement of the local electric-field intensity at the edges of the constriction results in a large decrease of the εSTO as shown in Figure d. This has two consequences that affect the electrostatic gating mechanism. First, it leads to a progressive saturation of the depleted carrier density in the channel, reducing the gating efficiency as VSG1,2 increases in magnitude. Second, it redistributes the electric-field lines toward the center of the constriction, flattening out the depletion profile. The first effect is reported in Figure e where the calculated polarization at the center of the channel (P) is plotted as a function of VSG1,2. The electric-field dependence of εSTO produces a deviation from the linear behavior one would obtain for εSTO = constant, resulting in a reduction of the depleted charge. Moreover, within the same side gate voltage range, the magnitude of the induced polarization is smaller for the case d = 200 nm than for d = 100 nm. This highlights the fact that the charge depletion is strongly dependent on the distance between the side gate electrodes and the channel. In Figure f we show how the steepness of the polarization profile across the channel is affected by the field dependence of εSTO. To evaluate this effect we consider the variation of the polarization between x = 0 nm and x = 20 nm, ΔP = P – P. For the case εSTO = constant, the magnitude of ΔP increases linearly with applied side gate voltage, representing a proportional scaling of the polarization profile. In contrast, for the case εSTO = f(E), it rapidly saturates at ∼5 μC/cm2. This limits the extent to which side gating can reduce the effective width of the channel, since the depletion profile is less steep due to the dielectric response of the STO, as opposed to the stronger sideways depletion that would be obtained if εSTO = constant (red and green curves in the inset of Figure f, respectively). This is in good agreement with previous reports on side gate electrodes at the LAO/STO interface, which show the electric field lines reaching the gas from below.[32] Therefore, the side gates are expected to act as an effective “local back gate” due to the proximity to the channel and can be used to locally modulate the carrier density at the nanoscale with the application of small voltages.

We first characterize the constrictions and the action of the two side gates through transport measurements in the normal state, at 1.5 K. Figure shows electrical measurements of devices Dev1 and Dev2, where the side gates are separated from the constriction by 200 and 100 nm, respectively. In both devices, the overall carrier density can be tuned by the application of a back gate voltage (VBG). The evolution of the four-probe resistance (R) across the constriction in Dev1 as a function of VSG1,2 for different VBG is shown in Figure a. At VBG= 10 V, R remains fairly unchanged within the side gate voltage range considered. This results from the fact that the change in carrier density Δn2D induced by the side gates is a small fraction of the total carrier density accumulated by the back gate. As the back gate voltage is decreased, the effect of the side gates becomes increasingly appreciable, and at VBG = 1 V, the side gates can completely deplete the channel.

Figure 3

(a) Four-probe resistance (R) of as a function of side gate voltage VSG1,2 measured for different VBG. (b) Map of R as a function of VSG1 and VSG2. The voltage step is 0.2 mV. (c) R as a function of side gate voltage. Dev1: VSG1 = VSG2 (green). Dev2: VSG1 = VSG2 (blue), VSG2 = 0 mV (red), and VSG1 = 0 mV (black).

Having established a range of VBG in which the voltages applied to the side gates induce appreciable changes in the transport through the constriction, we now study the individual action of the side gates. Figure b shows a 2D map of the four-probe resistance across the constriction of Dev2 as a function of VSG1 and VSG2. The action of each side gate on the constriction is identical, evidenced by the symmetry across the diagonal (gray line). This is also reflected in the good overlap between the red and black curves in Figure c, measured as SG1 and SG2 were individually driven from 0 to −50 mV, while keeping the other side gate at 0 mV. When both SG1 and SG2 are swept symmetrically, the resistance change is roughly twice as large (blue curve). This underlines the reliability of the patterning technique, where the action of the side gates is determined by the geometrical design. When comparing the induced change in resistance as a function of VSG1,2 for Dev1 and Dev2, we observe it to be much smaller for Dev1, where the side gate electrodes are patterned further away from the constriction. This corroborates the expectation that the tunability of the resistance strongly depends on d, in good agreement with the simulations from Figuree and f.

We now turn our attention to the study of the superconducting regime. In previous work it was shown that such constrictions act as a weak link between the two superconducting reservoirs, forming a Josephson junction (c-JJ type).[23] We first focus on the study and side gate modulation of transport through a single Josephson junction. In Figure a, the differential resistance dV/dI is plotted in color scale as a function of bias current Ibias and side gates voltage VSG1,2, i.e., in the symmetric side gating configuration (see Supporting Information for the study as a function of the independent side gate voltages). The measurement was performed at T = 50 mK with a fixed back gate voltage VBG = −11 V. It can be seen that, on average, the supercurrent range (black region) is reduced when VSG1,2 is driven to larger negative values, due to the consequent decrease of the electron carrier density. The corresponding values of critical current Ic as a function of VSG1,2 are plotted in Figure b. In the same graph, the differential conductance G is plotted in units of 2e2/h. Ic and G were determined from the differential resistance dV/dI, from the position of its maximum and its value at the maximum Ibias, respectively (see Supporting Information). It can be seen that both Ic and G fluctuate in an aperiodic manner as a function of applied side gate voltage. Measurements over several sweeping cycles (see Supporting Information) indicate that these fluctuations are time-independent and reproducible within the sample. Moreover, we observe that the fluctuation pattern of Ic is similar to that of G, indicating a common physical origin. We note the absence of such mesoscopic fluctuations in Dev2 at 1.5 K, due to the low Tgrowth and consequent high sheet resistance.

Figure 4

(a) Differential resistance (dV/dI) plotted as a function of bias current Ibias and side gate voltage VSG1,2, measured at VBG = −11 V and T = 50 mK. (b) Fluctuations of the conductance G and the critical current Ic as a function of applied side gate voltage VSG1,2.

The mesoscopic fluctuations of the critical current and conductance—so-called universal conductance fluctuations (UCF)—originate from the phase-coherent transport in a system with dimensions comparable to the phase coherence length (Lϕ), where only a limited number of inelastic scattering centers are involved.[33] Previous transport studies[34] at the LAO/STO interface have yielded a coherence length Lϕ ∼ 110 nm at 40 mK. From the AFM image we estimate a junction length L ≈ 500 nm (see Supporting Information); therefore, our c-JJs are expected to display mesoscopic fluctuations.

From the theoretical point of view, fluctuations in the critical current of a Josephson junction have been treated in two limits. For the short junction limit, where the junction length is much shorter than the superconductor coherence length (L ≪ ξ), Beenakker[35] has shown that the fluctuations are universal and that their amplitude depends only on the superconducting gap Δ: δIcrms ∼ eΔ/h. One does not expect our devices to fit this regime, since the measured length of the constriction L ≈ 500 nm is larger than previously reported values,[4,36] ξ ∼ 100 nm (at optimal doping). In the long junction limit, the reduction in the amplitude of the critical current fluctuations is caused by classical self-averaging due to inelastic scattering events, i.e., Lϕ < L. In addition, at finite temperatures thermal averaging needs to be taken into consideration when kBT > hD/Lϕ2, where D is the diffusion constant. The length associated with this dephasing mechanism is the thermal length . Al’tshuler and Spivak[37] have considered the theoretical description of the oscillations in critical current for the case Lϕ ≫ L ≫ LT. Since the aforementioned dephasing mechanisms should contribute to the reduction of the amplitude of mesoscopic oscillations in the same way, we consider an effective length Leff = (LT–2 + Lϕ–2)−1/2. Then, for the limit Leff ≫ w, t, where t ≈ 10 nm is the thickness of the 2DES,[36] the root-mean-square of the oscillations in critical current becomes[37]From the experimentally observed value δIcrms = 0.09 nA, we extract Leff ≈ 100 nm, which provides a relation between LT and Lϕ.

The amplitude of the conductance fluctuations now enables us to extract numerical values for these two length scales. In the microscopic theory of Lee, Stone, and Fukuyama,[33] the root-mean-square of the conductance oscillations (δGrms) was evaluated analytically only in the asymptotic regimes of Lϕ ≪ LT and LT ≪ Lϕ. At the LAO/STO interface, however, these two characteristic length scales are comparable,[38] namely, Lϕ ∼ LT. In order to facilitate comparison with the quasi-1D limit (w < LT, Lϕ < L), Beenakker and van Houten have proposed an approximate formula to interpolate between the two asymptotic regimesWe take α = β = 0.73, which recover the asymptotic results originally obtained in ref (33). From the data in Figure b we obtain δGrms = 0.086e2/h (see Supporting Information), which, together with Leff = 100 nm, yields Lϕ ≈ 170 nm and LT ≈ 120 nm. Hence, we can estimate a diffusion constant D ≈ 0.16 cm2/s and a Thouless energy ETh = Dℏ/Lϕ2 ≈ 0.4 μeV. As previously mentioned, we expect the studied device to belong to the long junction limit based on the value of L estimated from the AFM image. In this regime, the Thouless energy should be the dominant energy scale, i.e., ETh ≪ Δ. Within the range of side gate voltages considered, eIcR ≈ 20 μeV, which allows us to estimate Δ ≈ 7–14 μeV. Hence, the value of ETh determined from the combined analysis of the critical current and conductance fluctuations is in good agreement with the long junction limit.

Finally, we demonstrate the tunability offered by the side gates by integrating two side gated c-JJs in a superconducting loop to create a SQUID. Figure a shows an AFM image of the device which comprises a left (SGL) and right (SGR) side gate electrode to allow independent control of each c-JJ. If an external magnetic field is applied perpendicularly to the superconducting loop, the measured critical current oscillates periodically with the changes in phase at the two c-JJ junctions, as seen in Figure b. We plot the differential resistance in color scale as a function of current bias (Ibias) and applied (out-of-plane) magnetic field (B) for different combinations of side gate voltages. We start by investigating the case when no voltages are applied to the side gate electrodes (top panel), where periodic oscillations of the critical current as a function of the magnetic field are observed. The period of these oscillations is ΔB = 19 μT, which yields an effective loop area Aeff = h/2eΔB of approximately 8 × 8 μm2, indicated by the dashed line in Figure a. The difference between the estimated effective area and the area of the central insulating region (5 × 5 μm2) is expected and originates from flux-focusing effects due to the fact that the dimensions of the SQUID are smaller than the Pearl length (∼1 mm).[23] However, a small offset along the B-axis can be observed between the oscillations of positive and negative critical current. This asymmetry arises due to self-flux effects, which are particularly important for SQUIDs with a large kinetic inductance (Lk). This is indeed the case for SQUIDs made at the LAO/STO interface,[23] where the low superfluid density results in an exceptionally large kinetic inductance. The tunability of the superfluid density by electric field effect therefore provides a direct way to modulate the kinetic inductance through the application of a gate voltage. In our device, the reduced width of the c-JJs causes the kinetic inductance of each arm to be dominated by the weak link. The local modulation of the side gates therefore simultaneously affects the critical current of the weak link and the kinetic inductance of the arm. Thus, the independent tunability of each c-JJ should allow for the control of the asymmetry in the positive and negative critical current oscillations. By keeping VSGR fixed at 0 mV while driving VSGL to positive values (left column), the offset of the positive and negative Ic(B) along the B axis increases, as denoted by the blue lines connecting two maxima of both branches. In turn, when VSGL is kept fixed at 0 mV and VSGR made more positive (right column), the offset occurs in the opposite direction, as expected. This underlines the reliability of the side gate geometry in providing independent modulation of the c-JJs, thus enabling the control of the SQUID asymmetry.

Figure 5

(a) AFM image of the SQUID device which comprises a left (SGL) and right (SGR) side gate electrodes. Inset: c-JJ of the left arm and the respective side gate electrode. (b) Tunability of the SQUID oscillations. Left column: VSGR = 0 mV and different values of VSGL. Right column: VSGL = 0 mV and different values of VSGR. B0 is an experimentally determined offset in the magnetic field and has an uncertainty greater than one oscillation period.

In summary, we have realized nanoscale constrictions at the LAO/STO interface in conjunction with side gate electrodes, which are patterned in the 2DES itself, allowing for a single lithography step process. We have shown that such side gates allow for the reliable local modulation of transport across the constriction by electric field-effect. Finite element simulations show that, due to the electric-field dependence of the permittivity of STO, the action of these side gate electrodes is comparable to that of an effective “local back gate”. Transport measurements in the normal state have corroborated the reliability of the prepatterning technique used, by demonstrating a symmetric action of both side gates. In the superconducting regime, mesoscopic oscillations of conductance and Josephson supercurrent allow for the estimation of Lϕ and LT. Lastly, we integrate two side gated c-JJs in a superconducting loop to realize a SQUID. The subsequent control of the (a)symmetry of the SQUID response via the side gate electrodes underscores the reliability of our single-step technique. We demonstrate efficient local electrostatic control of the c-JJs, with the additional advantage of not requiring any post processing after the LAO growth. The results reported in this work open exciting perspectives for the study of quasi-one-dimensional superconductivity and for the realization of devices such as superconducting quantum point contacts.