| Literature DB >> 27725741 |
Yue Zhang1,2, Xueying Zhang1,2,3, Jingtong Hu4, Jiang Nan1,2, Zhenyi Zheng1,2, Zhizhong Zhang1,2, Youguang Zhang1,2, Nicolas Vernier3, Dafine Ravelosona3, Weisheng Zhao1,2,3.
Abstract
Racetrack memory (RM) has sparked enormous interest thanks to its outstanding potential for low-power, high-density and high-speed data storage. However, since it requires bi-directional domain wall (DW) shifting process for outputting data, the mainstream stripe-shaped concept certainly suffers from the data overflow issue. This geometrical restriction leads to increasing complexity of peripheral circuits or programming as well as undesirable reliability issue. In this work, we propose and study ring-shaped RM, which is based on an alternative mechanism, spin orbit torque (SOT) driven chiral DW motions. Micromagnetic simulations have been carried out to validate its functionality and exhibit its performance advantages. The current flowing through the heavy metal instead of ferromagnetic layer realizes the "end to end" circulation of storage data, which remains all the data in the device even if they are shifted. It blazes a promising path for application of RM in practical memory and logic.Entities:
Year: 2016 PMID: 27725741 PMCID: PMC5057157 DOI: 10.1038/srep35062
Source DB: PubMed Journal: Sci Rep ISSN: 2045-2322 Impact factor: 4.379
Figure 1(a) Conventional spin transfer torque (STT) driven racetrack memory (RM), in which current flows through the ferromagnetic (data storage) layer. (b) Real racetrack shape leads to short-circuit issue for STT driven RM. (c) Spin orbit torque (SOT) driven RM, in which current is injected in the heavy metal layer underneath the data storage layer. (d) Ring-shaped SOT driven RM schematic. Domain walls (DWs) can be nucleated and detected by magnetic tunnel junctions (MTJwrite and MTJread). Two gaps are introduced to avoid the short-circuit issue. Current flows through heavy metal layer and leaks partially through the ferromagnetic layer above the gap (see inset). The leakage current could also induce DW motions, which guarantees the continuation of data transfer.
Figure 2The top-view of the SOT driven chiral DW motions in the “Straight” and “Bend”.
Red represents + z magnetization, blue represents –z magnetization. (a–d) The “Straight”: 40 nm-wide and 1.28 μm-long Pt(2 nm)/CoFeB(0.6 nm)/MgO. DW motion velocity can reach 400 m/s with a current of 2 × 1011 A/m2. DW tilting occurs which agrees with experimental results. (e–h) The “Bend”: external diameter D is 1.024 μm, width d is 40 nm. The gap length of the heavy metal layer L is 100 nm. Current injected into the heavy metal layer for SOT part J is 3 × 1011 A/m2 and leakage current in the gap part inducing STT J is 1.4 × 1012 A/m2. The different directions of current for these two parts guarantee the uni-direction of DW motions.
Figure 316-bit ring-shaped RM schematic.
Two gaps and symmetric pinning sites (see inset) are used for ensuring the functionality and stability of the RM. J and J are 5 × 1012 A/m2 and 1 × 1012 A/m2. The length of gap is 100 nm each. 0.6 ns current pulses are sufficient for DW motions due to the inertia.
Figure 4(a) The dependence of the DW motion velocity (blue), the DW magnetization rotation angle (red) and the DW tilting angle (green) versus the applied current density. Due to the DW magnetization rotation and tilting, the velocity will be saturated with a high current density. (b) The dependence of the DW motion velocity versus the damping and DMI constants. Lower damping and stronger DMI allows higher velocity for low current densities.
Figure 5The dependence of the current density ratio of gap and ring parts versus the length ratio of gap and ring parts for different heavy metals.
Assuming a typical range of current density ratio (e.g. 1~10), a feasible range of length ratio can be obtained.
Figure 6The dependence of the energy consumption and latency per bit versus RM device capacity.
A 400 nm-long magnetic domain is regarded as a bit. The voltage supply is fixed to 0.53 V. A tradeoff relationship is found: higher device capacity achieves lower energy but higher latency.