In Situ XPS Chemical Analysis of MnSiO3 Copper Diffusion Barrier Layer Formation and Simultaneous Fabrication of Metal Oxide Semiconductor Electrical Test MOS Structures.

Copper/SiO2/Si metal-oxide-semiconductor (MOS) devices both with and without a MnSiO3 barrier layer at the Cu/SiO2 interface have been fabricated in an ultrahigh vacuum X-ray photoelectron spectroscopy (XPS) system, which allows interface chemical characterization of the barrier formation process to be directly correlated with electrical testing of barrier layer effectiveness. Capacitance voltage (CV) analysis, before and after tube furnace anneals of the fabricated MOS structures showed that the presence of the MnSiO3 barrier layer significantly improved electric stability of the device structures. Evidence of improved adhesion of the deposited copper layer to the MnSiO3 surface compared to the clean SiO2 surface was apparent both from tape tests and while probing the samples during electrical testing. Secondary ion mass spectroscopy (SIMS) depth profiling measurements of the MOS test structures reveal distinct differences of copper diffusion into the SiO2 dielectric layers following the thermal anneal depending on the presence of the MnSiO3 barrier layer.