| Literature DB >> 26648839 |
Narayan Srinivasa1, Nigel D Stepp1, Jose Cruz-Albrecht2.
Abstract
Neuromorphic hardware are designed by drawing inspiration from biology to overcome limitations of current computer architectures while forging the development of a new class of autonomous systems that can exhibit adaptive behaviors. Several designs in the recent past are capable of emulating large scale networks but avoid complexity in network dynamics by minimizing the number of dynamic variables that are supported and tunable in hardware. We believe that this is due to the lack of a clear understanding of how to design self-tuning complex systems. It has been widely demonstrated that criticality appears to be the default state of the brain and manifests in the form of spontaneous scale-invariant cascades of neural activity. Experiment, theory and recent models have shown that neuronal networks at criticality demonstrate optimal information transfer, learning and information processing capabilities that affect behavior. In this perspective article, we argue that understanding how large scale neuromorphic electronics can be designed to enable emergent adaptive behavior will require an understanding of how networks emulated by such hardware can self-tune local parameters to maintain criticality as a set-point. We believe that such capability will enable the design of truly scalable intelligent systems using neuromorphic hardware that embrace complexity in network dynamics rather than avoiding it.Entities:
Keywords: adaptive behavior; criticality; current balance; homeostasis; neuromorphic electronics; self-organization; spiking; synaptic plasticity
Year: 2015 PMID: 26648839 PMCID: PMC4664726 DOI: 10.3389/fnins.2015.00449
Source DB: PubMed Journal: Front Neurosci ISSN: 1662-453X Impact factor: 4.677
Figure 1(A) Tuning process required if synaptic weights or other low-level parameters need to be tuned for specific network inputs. (B) Tuning process for a self-tuning critical network. In this case, the network is tuned at a high level to select for critical dynamics that is adaptively maintained internally.
Figure 2(A) A typical configuration for interacting with the neuromorphic hardware, for instance when conducting a parameter search. Test software runs on a general purpose computer, which communicates with an FPGA over a USB connection. The connection allows software to upload networks to the chip, set hardware parameters, and perform spike-based input and output. (B) Flow chart detailing the parameter search process and its relation to each system component.