| Literature DB >> 25136662 |
Zhiwei Tang1, Bin Li2, Huosheng Li3, Zheng Xu4.
Abstract
Depth estimation becomes the key technology to resolve the communications of the stereo vision. We can get the real-time depth map based on hardware, which cannot implement complicated algorithm as software, because there are some restrictions in the hardware structure. Eventually, some wrong stereo matching will inevitably exist in the process of depth estimation by hardware, such as FPGA. In order to solve the problem a postprocessing function is designed in this paper. After matching cost unique test, the both left-right and right-left consistency check solutions are implemented, respectively; then, the cavities in depth maps can be filled by right depth values on the basis of right-left consistency check solution. The results in the experiments have shown that the depth map extraction and postprocessing function can be implemented in real time in the same system; what is more, the quality of the depth maps is satisfactory.Entities:
Mesh:
Year: 2014 PMID: 25136662 PMCID: PMC4066861 DOI: 10.1155/2014/363287
Source DB: PubMed Journal: ScientificWorldJournal ISSN: 1537-744X
Figure 13DTV system.
Figure 2Epipolar geometry.
Figure 3The 3DTV data representation using video plus depth.
Figure 4Depth map real-time extraction system structure diagram.
Figure 5The RTL schematic of comparison module in the unique matching detection.
Figure 6The sequential process about getting the parallax of the left view.
Figure 7The sequential process about getting the parallax of the right view.
Figure 8The extraction of the depth map.
The occupancy of FPGA resource.
| Item | Content | Remark | |
|---|---|---|---|
| FPGA type | EP2AGX260EF29C4 | Altera (Arria II GX260) | |
| FPGA resource | Total pins | 206/432 | 48% |
| Total block memory bits | 3004880/8755200 | 34% | |
| Total DSP block 18-bit elements | 0/736 | 0% | |
| Total GXB receiver channel PCS | 8/12 | 67% | |
| Total GXB receiver channel PMA | 8/12 | 67% | |
| Total GXB transmitter channel PCS | 8/12 | 67% | |
| Total GXB transmitter channel PMA | 8/12 | 67% | |
| Total PLLs | 2/6 | 33% | |
| Total DLLs | 1/2 | 50% | |
| PCIE hard IP | 1/1 | 100% | |
| Logic utilization | 34% | ||
| Combinational ALUTs | 35717/205200 | 17% | |
| Memory ALUTs | 24/102600 | <1% | |
| Dedicated logic registers | 60363/205200 | 29% | |
| Total registers | 60799 | ||