| Literature DB >> 22164058 |
Zong-Tao Li1, Tie-Jun Wu, Can-Long Lin, Long-Hua Ma.
Abstract
A new generalized optimum strapdown algorithm with coning and sculling compensation is presented, in which the position, velocity and attitude updating operations are carried out based on the single-speed structure in which all computations are executed at a single updating rate that is sufficiently high to accurately account for high frequency angular rate and acceleration rectification effects. Different from existing algorithms, the updating rates of the coning and sculling compensations are unrelated with the number of the gyro incremental angle samples and the number of the accelerometer incremental velocity samples. When the output sampling rate of inertial sensors remains constant, this algorithm allows increasing the updating rate of the coning and sculling compensation, yet with more numbers of gyro incremental angle and accelerometer incremental velocity in order to improve the accuracy of system. Then, in order to implement the new strapdown algorithm in a single FPGA chip, the parallelization of the algorithm is designed and its computational complexity is analyzed. The performance of the proposed parallel strapdown algorithm is tested on the Xilinx ISE 12.3 software platform and the FPGA device XC6VLX550T hardware platform on the basis of some fighter data. It is shown that this parallel strapdown algorithm on the FPGA platform can greatly decrease the execution time of algorithm to meet the real-time and high precision requirements of system on the high dynamic environment, relative to the existing implemented on the DSP platform.Entities:
Keywords: FPGA; computation complexity; coning and sculling compensation; parallelization design; strapdown algorithm
Year: 2011 PMID: 22164058 PMCID: PMC3231751 DOI: 10.3390/s110807993
Source DB: PubMed Journal: Sensors (Basel) ISSN: 1424-8220 Impact factor: 3.576
Figure 1.Intervals associated with strapdown algorithm.
Figure 2.Functional-block diagram of parallel strapdown algorithm.
Figure 3.Diagram of module M1.
Figure 4.Diagram of module M2.
Figure 5.Diagram of module M3.
Figure 6.Diagram of module M4.
Figure 7.Diagram of module M5.
Figure 8.Diagram of module M6.
Figure 9.Implementation of parallel strapdown algorithm base on FPGA.
Figure 10.Behavioral simulation waveform graph of parallel strapdown algorithm.
(a) Simulation results—gyro and accelerometer inputs; (b) Simulation results— attitude, velocity and position outputs.
| tn–1 | 7.3154e−5 | −4.0469e−6 | 7.0390e−6 | −1.4102e−4 | 3.3985e−4 | 9.9255e−3 |
| tn | 7.1058e−5 | 3.9166e−6 | 7.8809e−6 | −2.2112e−4 | 1.4560e−4 | 9.5916e−3 |
| (a) | ||||||
Resource utilization of parallel strapdown algorithm.
| 24,837 (3%) | 26,074 (7%) | 105 (12%) | |
| 687,360 | 343,680 | 864 |